US4198663A
Expired / Lapsed
US
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Digital signal recording system
Assignee: Fujitsu General Ltd
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Filing: 1978-05-08
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Granted: 1980-04-15
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Expires: 1998-05-08
Abstract
Abstract A digital signal recording system capable of a self-clocking and a peak detection. Binary data is represented by bi-level signal pulses which are spaced apart by a time interval which is a positive integral multiple of time interval of clock pulses (referred to as T 0 ). The width of the signal pulses at their one level is a constant value less than T 0 and where the time spacing between such signal pulses is greater than 2 T 0 , a selected number of pseudo pulses having the same pulse width as such signal pulses are inserted between the adjacent signal pulses with a time interval therefrom which is an odd multiple of T 0 /2.
Inventors
- 👤 Yasumasa Sugihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:50
CPC Classifications
G; G11; G11B; G11B23/00; G11B23/0007; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419; G11B20/1423
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
199 words
A digital signal modulation circuit comprising: an AND circuit having one input for receiving data signals and another input for receiving first clock pulse signals, a J-K flipflop circuit having its clock terminal connected to receive the output of said AND circuit and having a clear terminal connected to receive second clock pulse signals which are phase displaced 180° from said first clock pulse signals, a NOT circuit having an input for receiving the data signals, a gate pulse forming circuit connected to the output of said NOT circuit to receive therefrom inverted data signals and responsive to only the rising end of the inverted data signals for producing time-delayed gate pulse signals which are delayed by a time interval less than the period of the clock pulse signals, another AND circuit having one input connected to receive the time-delayed gate pulse signals and another input for receiving the second clock pulse signals, another J-K flipflop circuit having its clock terminal connected to the output of said another AND circuit and having its clear terminal connected to receive the first clock pulse signals, and an OR circuit connected to receive the output signals from both said J-K flipflop circuits.
Claim 2
Dependent Claim
199 words
A digital signal modulation circuit comprising: an AND circuit having one input for receiving data signals and another input for receiving first clock pulse signals, a J-K flipflop circuit having its clock terminal connected to receive the output of said AND circuit and having a clear terminal connected to receive second clock pulse signals which are phase displaced 180° from said first clock pulse signals, a NOT circuit having an input for receiving the data signals, a gate pulse forming circuit connected to the output of said NOT circuit to receive therefrom inverted data signals and responsive to only the rising end of the inverted data signals for producing time-delayed gate pulse signals which are delayed by a time interval less than the period of the clock pulse signals, another AND circuit having one input connected to receive the time-delayed gate pulse signals and another input for receiving the second clock pulse signals, another J-K flipflop circuit having its clock terminal connected to the output of said another AND circuit and having its clear terminal connected to receive the first clock pulse signals, and an OR circuit connected to receive the output signals from both said J-K flipflop circuits.
Claim 3
Dependent Claim
58 words
A digital signal modulation circuit according to claim 1 in which said gate pulse forming circuit comprises an integrator connected to the output of said NOT circuit for integrating the inverted data signals, and an AND circuit having one input connected to the output of said integrator and another input connected to the output of said NOT circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-04-15 | 1983-10-15 | 1984-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-04-15 | 1987-10-15 | 1988-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-04-15 | 1991-10-15 | 1992-04-15 | $7700.00 | Window Closed / Lapsed |