Photodetector timer network

Claim 2

A photodetector timer network, comprising: a photodetector circuit for generating an electrical detector signal responsive to a decreasing light level; a hold-off circuit for receiving the detector signal from the photodetector circuit and passing a responsive signal; a flip-flop network having a set and a reset input with the set input receiving the responsive signal from the hold-off circuit such that the flip-flop is set pursuant to the responsive signal and generates an output control signal pursuant to the setting of the flip-flop network; a first timing circuit coupled to the flip-flop network to receive the control signal, the timing cycle of the timing circuit being responsive to the control signal and generating reset signals for the flip-flop network; and p1 a load switcher network coupled to the flip-flop network and intermediate an external electrical load and an external electrical power source, the load switcher network being responsive to the control signal for controlling electrical power from the power source to the external load; the hold-off network being further coupled to the output of the flip-flop network to receive the control signal and delay the flip-flop network from being set responsive to the detector signal if the external load is deenergized under low light conditions within a predetermined time period.

Claim 3

A photodetector timer network of claim 1 wherein the photodetector circuit includes a voltage divider having a photocell with the output of the voltage divider being a function of the illumination of said photocell and a snap-acting amplifier coupled intermediate to the voltage divider and the hold-off circuit.

Claim 4

A photodetector timer network of claim 2 wherein the photodetector circuit further includes capacitive elements across the voltage divider for suppressing electric noise.

Claim 5

A photodetector timer network of claim 1 wherein the hold-off circuit is further adapted to receive a second signal which second signal is responsive to the conductive state of the flip-flop network and for holding-off the responsive signal for a period after the flip-flop network is reset.

Claim 6

A photodetector timer network of claim 4 wherein the hold-off circuit inhibits the transfer of the detector signal to the flip-flop during a time period determined by a charge-discharge means responsive to the flip-flop output control signal.

Claim 7

A photodetector timer network of claim 1 wherein the timing circuit includes means for generating time signals for controlling resetting of the flip-flop to interrupt generation of control signals after a predetermined time period.

Claim 8

A photodetector timer network of claim 6 wherein the timing circuit includes an oscillator and a counter, said counter being set pursuant to the control signal and generating a predetermined timing signal pursuant to a number of cycles of said oscillator after the initial control signal.

Claim 9

A photodetector timer network of claim 5 wherein the hold-off circuit includes a resistive element intermediate the photodetector circuit and the flip-flop network, a unidirectional control gate coupled to said resistive element and to a capacitive element, said capacitive element being coupled to a reference potential, and the junction of said gate and capacitive element being coupled through a resistive element to the output of the flip-flop network to receive the control signal.

Claim 10

A photodetector timer network of claim 7 wherein the timing circuit includes an oscillator and a counter network for counting cycles of said oscillator, said counter being set pursuant to the control signal and generating a plurality of timing signals pursuant to a predetermined number of cycles of said oscillator after being set by the control signal.

Claim 11

A photodetector timer network of claim 1 wherein the load switcher network includes a bidirectional current control gate with one gate tied to a transistor and a voltage reference source and the other gate tied to an output terminal to be engaged by a load, said transistor being coupled to the output of the flip-flop network to receive the control signal.

Claim 12

A photodetector timer network of claim 1 wherein the reset circuit of the flip-flop includes means to reset the flip-flop after temporary loss of the external power source.

Claim 13

A photodetector timer network of claim 10 wherein the reset terminal of the flip-flop is further coupled to a power supply through a reactive circuit resetting the flip-flop after an interruption of electrical power to the network.

Claim 14

A photodetector timer network of claim 10 wherein the hold-off circuit is further adapted to recieve a second signal which second signal is responsive to the conductive state of the flip-flop network for holding-off the responsive signal for a period after the flip-flop network is reset.

Claim 15

A photodetector timer network of claim 13 wherein the hold-off circuit includes a first resistive element intermediate the photodetector circuit and the flip-flop network, a unidirectional control gate coupled to said first resistive element and to a first capacitive element, said first capacitive element being coupled to a reference potential, the junction of said gate and first capacitive element being coupled through a second resistive element to the output of the flip-flop network.

Claim 16

A photodetector timer network of claim 12 wherein the flip-flop network further includes a resistance-capacitance path of low resistance intermediate the reset input and the power source and a high resistance path intermediate the reset input and ground reference.

Claim 17

A photodetector timer network of claim 1 wherein the timing circuit includes means to randomly select one of a set of different timing signals.

Claim 18

A photodetector timer network of claim 16 wherein the timing circuit includes an oscillator and a time counter, said counter being set pursuant to the control signal and generating a plurality of different timing signals timed pursuant to a predetermined count of cycles of said oscillator after the initial control signal; and logic circuitry connected to receive said plurality of timing signals, the control signal and oscillator signal, the logic circuitry being adapted to deliver a reset signal to the flip-flop network upon the random simultaneous timing of the control signal, oscillator signal and one of said timing signals.

Claim 19

A photodetector timer network of claim 17 wherein the logic circuitry includes a first AND gate for receiving the control signal and oscillator signal, a first flip-flop connected to the output of said first AND gate, a second flip-flop connected to the output of the first flip-flop, a second AND gate connected to the output of the first flip-flop, to the second flip-flop and to said time counter, a third logic AND gate connected to the output of the second flip-flop and said time counter, and a logic OR gate tied to the outputs of the second and third AND gates and said time counter, the output of said OR gate extending to the reset of the flip-flop network.

Claim 20

A photodetector timer of claim 1 further including a second timing circuit for randomly interrupting the timing cycle of the first timing circuit.

Claim 21

A photodetector timer network of claim 19 wherein the first timing circuit includes a first oscillator and a time counter for generating a first set of time signals and a second set of time signals, the time interval of said second set of time signals being substantially less than that of the first set of time signals, and means for delivering select ones of the first set of time signals to the reset of the flip-flop network; and a second timing circuit for receiving the second set of time signals and including two logic AND gates interconnected to said time counter to receive said second set of time signals and to the output of a second flip-flop to select which of said two AND gates pass selected ones of said second set of time signals to the input of a presettable counter whose input is connected to the two logic AND gates and whose output is connected to the input of said second flip-flop, said presettable counter having a plurality of preset input terminals, said preset input terminals being connected to a gatable oscillator-counter network, differentiating means intermediate the output of said presettable counter and said second flip-flop to differentiate the output of the presettable counter, a squaring amplifier intermediate said differentiating means and the input to said gatable oscillator-counter and a load terminal of said presettable counter to preset said presettable counter and freeze said oscillator-counter responsive to the output of said presettable counter.