US4196787A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Desired speed signal memory circuit for an automobile speed control system
Assignee: Aisin Corp
•
Filing: 1978-04-14
•
Granted: 1980-04-08
•
Expires: 1998-04-14
Abstract
Abstract A desired automobile speed signal memory circuit for an automobile speed control system to maintain actual automobile speed constant at a desired speed. The memory circuit memorizes an actual automobile speed signal at the moment a desired speed set switch is closed. This memorized automobile speed signal is then used as a reference signal by the automobile speed control system to keep the actual automobile speed constant. The memory circuit has a capacitor which memorizes the desired speed signal, a first FET which forms a memorization loop with the capacitor upon the closure of the desired speed set switch, and a second FET which supplies the memorized desired speed signal on the capacitor in an impedance conversion mode as the reference signal used by the automobile speed control system to maintain constant the speed of the automobile.
Inventors
- 👤 Naoji Sakakibara
- 👤 Shoji Kawata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:12
CPC Classifications
B; B60; B60K; B60K31/00; B60K31/06; B60K31/10; B60K31/102; B60K31/105
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
208 words
In an automobile speed control system having an actual speed signal input terminal, means for providing an actual speed signal, a desired speed signal memory circuit, comparing means for comparing the desired and actual speed signals and having first and second input terminals for receiving said actual and desired speed signals, respectively, and means responsive to the comparison for controlling a throttle valve of the automobile, the improvement comprising feedback circuit means for providing at an output terminal thereof a feedback signal substantially indicating the position of the throttle valve, said output terminal being connected to said first input terminal for supplying the feedback signal to said comparing means; and wherein said desired speed signal memory circuit comprises: a memory capacitor having a terminal; a first field effect transistor having an input terminal connected to the actual speed signal input terminal and an output terminal connected to the terminal of said memory capacitor; and a second field effect transistor, the base of which is connected to the terminal of said memory capacitor, for supplying the desired speed signal to said second input terminal of said comparing means; the input terminal of said first field effect transistor also being connected to the output terminal of said feedback circuit means.
Claim 2
Dependent Claim
208 words
In an automobile speed control system having an actual speed signal input terminal, means for providing an actual speed signal, a desired speed signal memory circuit, comparing means for comparing the desired and actual speed signals and having first and second input terminals for receiving said actual and desired speed signals, respectively, and means responsive to the comparison for controlling a throttle valve of the automobile, the improvement comprising feedback circuit means for providing at an output terminal thereof a feedback signal substantially indicating the position of the throttle valve, said output terminal being connected to said first input terminal for supplying the feedback signal to said comparing means; and wherein said desired speed signal memory circuit comprises: a memory capacitor having a terminal; a first field effect transistor having an input terminal connected to the actual speed signal input terminal and an output terminal connected to the terminal of said memory capacitor; and a second field effect transistor, the base of which is connected to the terminal of said memory capacitor, for supplying the desired speed signal to said second input terminal of said comparing means; the input terminal of said first field effect transistor also being connected to the output terminal of said feedback circuit means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-04-08 | 1983-10-08 | 1984-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-04-08 | 1987-10-08 | 1988-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-04-08 | 1991-10-08 | 1992-04-08 | $7700.00 | Window Closed / Lapsed |