Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
588 words
A digital control device controlling a multiphase thyristor-pulse d.c. converter and comprising: a master oscillator; a clock pulse counter having an input connected to an output of said master oscillator, and outputs; a control unit; a reversible counter having add and subtract inputs respectively connected to add and subtract outputs of said control unit, and outputs; a first decoder having inputs connected to respective outputs of said clock pulse counter, main outputs equal in number to the number of phases of the converter, and auxiliary outputs alternating with said main outputs, the number of said auxiliary outputs being one less than the number of said main outputs; a second decoder having inputs connected to respective outputs of said clock pulse counter and to respective outputs of said reversible counter, main outputs equal in number to the number of phases of the converter, and auxiliary outputs alternating with said main outputs, the number of said auxiliary outputs being one less than the number of said main outputs; a NOT gate having an input and an output; an OR gate having inputs connected to an emergency output of a respective phase of the converter, and an output connected to said input of said NOT gate; a first recalculation unit including main AND gates and emergency AND gates; said main AND gates of said first recalculation unit being equal in number to the number of phases of the converter, each main AND gate having a first input connected to said output of said NOT gate, a second input connected to a respective main output of said first decoder, and an output connected to a control electrode of a main thyristor of a respective phase of the converter; said emergency AND gates of said first recalculation unit being divided into groups whose number is equal to the number of phases of the converter, the number of said emergency AND gates in each group being equal to the number of auxiliary outputs of said first decoder, each emergency AND gate having a first input connected to a respective auxiliary output of said first decoder, a second input connected to said emergency output of a respective phase of the converter, the control electrode of a main thyristor of one of the other phases of the converter being connected to an output of a respective emergency AND gate of a respective group; a second recalculation unit including main AND gates and emergency AND gates; said main AND gates of said second recalculation unit being equal in number to the number of phases of the converter, each main AND gate having a first input connected to the output of said NOT gate, a second input connected to a respective main output of said second decoder, and an output connected to a control electrode of a switching thyristor of a respective phase of the converter; and said emergency AND gates of said second recalculation unit being divided into groups whose number is equal to the number of phases of the converter, the number of said emergency AND gates in each group being equal to the number of auxiliary outputs of said second decoder, each emergency AND gate having a first input connected to a respective auxiliary output of said second decoder, a second input connected to said emergency output of a respective phase of the converter, the control electrode of a switching thyristor of one of the other phases of the converter being connected to an output of a respective emergency AND gate of a respective group.
Claim 2
Dependent Claim
588 words
A digital control device controlling a multiphase thyristor-pulse d.c. converter and comprising: a master oscillator; a clock pulse counter having an input connected to an output of said master oscillator, and outputs; a control unit; a reversible counter having add and subtract inputs respectively connected to add and subtract outputs of said control unit, and outputs; a first decoder having inputs connected to respective outputs of said clock pulse counter, main outputs equal in number to the number of phases of the converter, and auxiliary outputs alternating with said main outputs, the number of said auxiliary outputs being one less than the number of said main outputs; a second decoder having inputs connected to respective outputs of said clock pulse counter and to respective outputs of said reversible counter, main outputs equal in number to the number of phases of the converter, and auxiliary outputs alternating with said main outputs, the number of said auxiliary outputs being one less than the number of said main outputs; a NOT gate having an input and an output; an OR gate having inputs connected to an emergency output of a respective phase of the converter, and an output connected to said input of said NOT gate; a first recalculation unit including main AND gates and emergency AND gates; said main AND gates of said first recalculation unit being equal in number to the number of phases of the converter, each main AND gate having a first input connected to said output of said NOT gate, a second input connected to a respective main output of said first decoder, and an output connected to a control electrode of a main thyristor of a respective phase of the converter; said emergency AND gates of said first recalculation unit being divided into groups whose number is equal to the number of phases of the converter, the number of said emergency AND gates in each group being equal to the number of auxiliary outputs of said first decoder, each emergency AND gate having a first input connected to a respective auxiliary output of said first decoder, a second input connected to said emergency output of a respective phase of the converter, the control electrode of a main thyristor of one of the other phases of the converter being connected to an output of a respective emergency AND gate of a respective group; a second recalculation unit including main AND gates and emergency AND gates; said main AND gates of said second recalculation unit being equal in number to the number of phases of the converter, each main AND gate having a first input connected to the output of said NOT gate, a second input connected to a respective main output of said second decoder, and an output connected to a control electrode of a switching thyristor of a respective phase of the converter; and said emergency AND gates of said second recalculation unit being divided into groups whose number is equal to the number of phases of the converter, the number of said emergency AND gates in each group being equal to the number of auxiliary outputs of said second decoder, each emergency AND gate having a first input connected to a respective auxiliary output of said second decoder, a second input connected to said emergency output of a respective phase of the converter, the control electrode of a switching thyristor of one of the other phases of the converter being connected to an output of a respective emergency AND gate of a respective group.