Key code generator

Claim 1

A Key code generator comprising: first and second clocks, each producing a respective predetermined clock output; a plurality of key code generator circuits, each key code generator circuit respectively corresponding to one of a corresponding plurality of key switches, and each key code generator circuit comprised of a first memory circuit for storing therein the state of the corresponding key switch by means of said predetermined first clock, a second memory circuit for storing therein the output from said first memory circuit, a transition detector circuit for detecting the change of state of the key switch to its depressed and then released state from the output from said first and second memory circuits, means for generating a key code corresponding to the key switch from the output from the transition detector circuit, and means for applying the first clock to the second memory circuit to complete the key code generation; priority means for achieving the transition detecting operation in the key code generator circuit group in accordance with a predetermined priority to thereby generate the key codes from the key code generator circuits in decreasing order of priority while temporarily inhibiting the outputs from the transition detector circuits of lower priority to prevent the key code generation therefrom; control means for inhibiting the key code generation based on the depression of a key in favor of the key code generation based on the release of a key; and a time division circuit comprised of an (m×n) key switch matrix circuit composed of said plurality of key switches, each key switch respectively connected with one of the key code generator circuits, means for transferring key switch information from the key switch matrix circuit for each octave, the key switch information being time divided into m groups of switches with n switches in each group by said second clock which is of a lower speed than said first clock, and a control circuit for sequentially storing at said lower speed the key switch information into the key code generator circuits, and wherein said key code generator circuits are correspondingly divided into m blocks, each block composed of n key code generator circuits.