US4194087A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Control circuit and FM stereo receiver using same
Assignee: Trio KK
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Filing: 1978-05-08
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Granted: 1980-03-18
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Expires: 1998-05-08
Abstract
Abstract Circuitry for generating from an input signal having leading and trailing edges at least two output control signals where the leading and trailing edges of the first one of the two output control signals respectively precede and follow the leading and trailing edges of the second one of the two output control signals, the circuitry comprising a first transistor responsive to the input signal; time constant circuit means having a predetermined time constant connected to the first transistor; a second and third transistors responsive to the first transistor and the time constant circuit means; bias means for so establishing different operating voltages for the second and third transistors that, upon application of the input signal to the first transistor, the first and second output control signals are respectively outputted by second and third transistors due to the fact that they are actuated at different times by the output signal from the first transistor and the time constant circuit depending on whether the input signal is rising or falling. Also an FM stereo receiver incorporating the above circuitry.
Inventors
- 👤 Kaku Sakaida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:27
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/06; H04B1/16; H04B1/1646; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/34; H03G3/341; H03G3/348
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
168 words
Circuitry for generating from an input signal having leading and trailing edges at least two output control signals where the leading and trailing edges of the first one of said two output control signals respectively precede and follow the leading and trailing edges of the second one of said two output control signals, said circuitry comprising a first transistor responsive to said input signal; time constant circuit means having a predetermined time constant connected to said first transistor; a second and third transistors responsive to said first transistor and said time constant circuit means; bias means for so establishing different operating voltages for said second and third transistors that, upon application of said input signal to said first transistor, said first and second output control signals are respectively outputted by second and third transistors due to the fact that they are actuated at different times by the output signal from said first transistor and said time constant circuit depending on whether the input signal is rising or falling.
Claim 2
Dependent Claim
168 words
Circuitry for generating from an input signal having leading and trailing edges at least two output control signals where the leading and trailing edges of the first one of said two output control signals respectively precede and follow the leading and trailing edges of the second one of said two output control signals, said circuitry comprising a first transistor responsive to said input signal; time constant circuit means having a predetermined time constant connected to said first transistor; a second and third transistors responsive to said first transistor and said time constant circuit means; bias means for so establishing different operating voltages for said second and third transistors that, upon application of said input signal to said first transistor, said first and second output control signals are respectively outputted by second and third transistors due to the fact that they are actuated at different times by the output signal from said first transistor and said time constant circuit depending on whether the input signal is rising or falling.
Claim 3
Dependent Claim
11 words
Circuitry as in claim 1 where said transistors are NPN transistors.
Claim 4
Dependent Claim
12 words
Circuitry as in claim 1 where said transistors are field effect transistors.
Claim 5
Dependent Claim
68 words
Circuitry as in claim 1 where each said transistor has an input and output terminal and control terminal, said input signal being applied to the control terminal of said first transistor and said output signal from said first transistor and said time constant circuit being applied from the output terminal of said first transistor to the control terminals of said second and third transistors via said bias means.
Claim 6
Dependent Claim
16 words
Circuitry as in claim 4 where the input terminals of said transistors are connected in common.
Claim 7
Dependent Claim
167 words
An FM stereo receiver having at least one output terminal comprising means responsive to an FM signal including detecting means for detecting from the FM signal a composite stereo signal frequency modulated thereon; a phase-locked loop demodulator having at least two output terminals and a voltage controlled oscillator for demodulating said composite stereo signal to obtain discrete stereo signals; at least two switching means respectively disposed between the two outputs of said phase-locked loop demodulator and said receiver output terminal; signal detecting means responsive to said composite stereo signal for detecting the presence or absence of said FM signal; circuit means as defined in claim 1 responsive to said signal detecting means; means responsive to said first output control signal for actuating said voltage controlled oscillator when said FM signal is present; and means responsive to said second output control signal for actuating said switching means when said FM signal is present whereby undesired radiation from said voltage controlled oscillator is reduced and shock noise is lessened.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-03-18 | 1983-09-17 | 1984-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-03-18 | 1987-09-17 | 1988-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-03-18 | 1991-09-17 | 1992-03-18 | $7700.00 | Window Closed / Lapsed |