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US4193300A Expired / Lapsed US ⏱️ 0.0 years remaining

Signal linearizing circuit for internal combustion engines

Assignee: Robert Bosch GmbH
•
Filing: 1978-07-17
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Granted: 1980-03-18
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Expires: 1998-07-17
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Abstract

Abstract A circuit arrangement for linearizing the output signal of a probe such as a hot-wire probe used for quantitative air measurement in the intake manifold of an internal combustion engine which includes a log stage, a multiplier stage and an antilog stage connected in series, the probe signal being applied to the input of the log stage and the linearized output signal taken from the output of the antilog stage.

Inventors

  • 👤 Cornelius Peter

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 20:18
CPC Classifications
G; G01; G01F; G01F1/00; G01F1/68; G01F1/696; G01F1/698

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 87 words
A circuit arrangement for linearizing the output signal of a quantitative measuring probe preferably arranged as a bridge circuit including a temperature-dependent resistor and adapted particularly for the measurement of the quantity of air flowing in the intake manifold of an internal combustion engine, comprising in combination, a log stage, a multiplier stage and an antilog stage connected in series and means for feeding the probe signal to the input of said log stage to produce a linearized output signal at the output of said antilog stage.
Claim 2
Dependent Claim 87 words
A circuit arrangement for linearizing the output signal of a quantitative measuring probe preferably arranged as a bridge circuit including a temperature-dependent resistor and adapted particularly for the measurement of the quantity of air flowing in the intake manifold of an internal combustion engine, comprising in combination, a log stage, a multiplier stage and an antilog stage connected in series and means for feeding the probe signal to the input of said log stage to produce a linearized output signal at the output of said antilog stage.
Claim 3
Dependent Claim 37 words
A circuit arrangement according to claim 1, including means for setting the multiplication factor of said multiplier stage to a value which is optimal for the linearity of the output signal of the circuit arrangement for linearization.
Claim 4
Dependent Claim 35 words
A circuit arrangement according to claim 1 including means for setting the multiplication factor of said multiplier stage to a value related to the electrical characteristics of the adjacent stages and especially the subsequent stages.
Claim 5
Dependent Claim 41 words
A circuit arrangement according to claim 1, wherein at least the active components of said log stage, said multiplier stage and said antilog stage are arranged in close mutual temperature contact to compensate for the temperature characteristics of the individual stages.
Claim 6
Dependent Claim 83 words
A circuit arrangement according to claim 1, including means for producing a reference voltage to provide a third potential in addition to the positive and zero potentials in the circuit arrangement, means for feeding said reference voltage to at least said log stage and said antilog stage, the difference between the voltage of the probe signal and said reference voltage forming a logarithm and the value of said reference voltage being selected so as to be equal to the optimum value for linerization.
Claim 7
Dependent Claim 143 words
A circuit arrangement according to claim 1 including a first transistor, a second transistor and a third transistor, the emitters of said transistors being connected together and connected through a resistor to ground, means for feeding said probe signal directly to the collector of said first transistor, means including a first amplifier stage for feeding said probe signal to the base of said first transistor, a second amplifier stage connected between the collector and the emitter of said second transistor, means for connecting the base of said third transistor to the junction between the base of said first transistor and the output of said first transistor and the output of said first amplifier stage, the collector of said third transistor forming the output for said linearized output signal and the bases of said first and second transistors both connected to one reference potential.
Claim 8
Dependent Claim 23 words
A circuit arrangement according to claim 1 including a controllable current source having a transistor connected to the output of said antilog stage.

References Cited (Backward Citations)

US3363462A Cited
US3595079A Cited
US4043196A Cited
US4070908A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1983-03-18 1983-09-17 1984-03-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1987-03-18 1987-09-17 1988-03-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1991-03-18 1991-09-17 1992-03-18 $7700.00 Window Closed / Lapsed

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