Voltage regulator and regulator buffer

Claim 2

A voltage regulator which compensates for variations in power supply voltage of 2.7 V±30% between said power supply and a reference voltage and which supplies CML devices with a constant voltage, comprising: a plurality of matched transistors connected in parallel with each other but connected in series between said power supply voltage and said reference voltage so as to provide paths of equal current therebetween, an output node and resistance means in series between said transistors and said power supply voltage, circuit means including a pair of transistors connected in series between said power supply voltage and said reference voltage so as to be responsive to variations in supply voltage, the base of one of said plurality of transistors being connected between said pair of transistors whereby said one transistor is responsive to voltage variations in said circuit means and will shunt variations in current due to the variations of power supply voltage through said one transistor holding the current through the other of the plurality of transistors constant so that the voltage at said output node is held constant.

Claim 3

The voltage regulator as claimed in claim 1 wherein said plurality of matched transistors include four NPN transistors whose collectors are connected in common to said output node, and whose emitters are connected in common to said reference voltage, the first of said four transistors has its collector also shorted to its emitter and also connected to the base of the second of said four transistors, and the second of said four transistors has its collector connected to the base of the third transistor of said four transistors.

Claim 4

The voltage regulator as claimed in claim 2 further including resistance means connected between said pair of transistors and power supply voltage and wherein said pair of transistors are NPN transistors with the collector of one of said pair connected to said last mentioned resistance means and to its base and wherein the second of said pair has its collector connected to the emitter of said one of said pair and to its base and wherein the emitter of said second transistor of said pair is connected to reference voltage.

Claim 5

The regulator as claimed in claim 1 further including a regulator buffer in combination therewith comprising; a buffer output node, a first transistor connected in series between said power supply voltage and said reference voltage, the base of said first transistor being connected to the output node of said regulator, a pair of resistance means connected between said first transistor and said power supply voltage, a first pair of transistors connected in parallel with said first transistor and in series with said supply voltage, reference voltage, and one of said resistance means, and circuit means including a second pair of transistors connected in series between said power supply voltage and said reference voltage so as to be responsive to variations in power supply voltage, the base of one of said first pair of transistors being connected between said second pair of transistors, whereby said one of said first pair of transistors is responsive to voltage variations in said circuit means and will shunt current therethrough holding the current through said first transistor constant so that the voltage in said buffer output node is held constant.

Claim 6

The regulator as claimed in claim 3 further including a regulator buffer in combination therewith, comprising: a buffer output node, a first transistor connected in series between said power supply voltage and said reference voltage, the base of said first transistor being connected to the output node of said regulator, a pair of resistance means connected between said first transistor and said power supply voltage, a first pair of transistors connected in parallel with said first transistor and in series with said supply voltage, reference voltage, and one of said resistance means, and circuit means including a second pair of transistors connected in series between said power supply voltage and said reference voltage so as to be responsive in variations in power supply voltage, the base of one of said first pair of transistors being connected between said second pair of transistors, whereby said one of said first pair of transistors is responsive to voltage variations in said circuit means and will shunt current therethrough holding the current through said first transistor constant so that the voltage in said buffer output node is held constant.

Claim 7

The regulator and regulator buffer as claimed in claim 5 wherein all of the transistors of said buffer are NPN transistors and wherein the emitter of said first transistor is connected to reference voltage through a third resistance means and its collector is connected to the buffer output node through one of said pair of resistance means, and wherein the collectors of said first pair of transistors are connected to said buffer output node and wherein first transistor of said second pair of transistors has its collector connected to power supply voltage and its emitter connected to the collector of the second transistor of said second pair, and wherein the collector of said second transistor of said second pair is connected to its base and its emitter is connected to reference voltage.