US4184630A
Expired / Lapsed
US
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Verifying circuit operation
Assignee: International Business Machines Corp
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Filing: 1978-06-19
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Granted: 1980-01-22
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Expires: 1998-06-19
Abstract
Abstract A polynomial based apparatus, such as an error correcting apparatus, is checked by repeatedly supplying test bits to the apparatus. On even cycles, the modulo two sum of the signal contents should be zero, while on odd cycles it should be equal to the pattern used for test purposes.
Inventors
- 👤 Donald R. Woodward
- 👤 John W. Marshall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:08
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277; G06F11/27
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
96 words
The method of testing logic apparatus embodying a polynomial equation as a design base, the steps of: repeatedly supplying a given set of test bits to said apparatus, upon predetermined ones of said repeated supply of test bits, extract the signal contents from said apparatus, if such one repeated supply is an even numbered repetition, check said extracted signals for a sum of zero, if such one repeated supply is an odd numbered repetition, check said extracted signals for an equality with said test bits, and signal an error condition upon a failure of said check.
Claim 2
Independent Claim
96 words
The method of testing logic apparatus embodying a polynomial equation as a design base, the steps of: repeatedly supplying a given set of test bits to said apparatus, upon predetermined ones of said repeated supply of test bits, extract the signal contents from said apparatus, if such one repeated supply is an even numbered repetition, check said extracted signals for a sum of zero, if such one repeated supply is an odd numbered repetition, check said extracted signals for an equality with said test bits, and signal an error condition upon a failure of said check.
Claim 3
Dependent Claim
20 words
The method of claim 1 including selecting said predetermined repeated repetitions to include both an odd and an even repetition.
Claim 4
Dependent Claim
19 words
The method of claim 1 including checking during each and every one of said repeated supply of test bits.
Claim 5
Dependent Claim
59 words
The method of claim 3, further including the steps of: simultaneously testing a plurality of units in said apparatus, during said even cycles testing for zero by modulo two comparing signal contents of all units, and during said odd cycles testing for equality by modulo two summing the signal contents of all units for comparison with said test bits.
Claim 6
Dependent Claim
48 words
The method set forth in claim 4 wherein said apparatus embodies a polynomial expressable in a Galois Field, said units in said apparatus exhibiting a shift property and during each such repeated supply of test bits also shift signal contents of said units in accordance with said polynomial.
Claim 7
Dependent Claim
118 words
Error correction apparatus having a plurality of syndrome generators and means interconnecting said syndrome generators, and embodying a polynomial in a Galois Field, characterized in that: means connected to said plurality of syndrome generators for supply digital signals thereto for enabling generation of predetermined repetitive patterns alternately yielding zero and non-zero signal contents therein, first logic means connected to said plurality of syndrome generators to test said syndrome generators for signal contents representing zero, second logic means connected to said plurality of syndrome generators to test said syndrome generators for a signal content equal to a predetermined number, both said logic means including modulo-2 operative circuits, and control means connected to said logic means for alternatively actuating same.
Claim 8
Dependent Claim
118 words
Error correction apparatus having a plurality of syndrome generators and means interconnecting said syndrome generators, and embodying a polynomial in a Galois Field, characterized in that: means connected to said plurality of syndrome generators for supply digital signals thereto for enabling generation of predetermined repetitive patterns alternately yielding zero and non-zero signal contents therein, first logic means connected to said plurality of syndrome generators to test said syndrome generators for signal contents representing zero, second logic means connected to said plurality of syndrome generators to test said syndrome generators for a signal content equal to a predetermined number, both said logic means including modulo-2 operative circuits, and control means connected to said logic means for alternatively actuating same.
Claim 9
Dependent Claim
51 words
Error correction as set forth in claim 6, further including, modulo-two counter means in said control means for indicating odd and even cycles of operation of said plurality of syndrome generators, and said control means actuating said first and second logic means during said even and odd cycles of operation, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-01-21 | 1983-07-23 | 1984-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-01-21 | 1987-07-23 | 1988-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-01-21 | 1991-07-23 | 1992-01-22 | $7700.00 | Window Closed / Lapsed |