Random number generator

Claim 2

A generator for producing random binary bits comprising in combination, means for producing a random noise electrical signal, means coupled to the output of said signal producing means for converting said random noise electrical signal into a variable width square wave signal having polarities proportional to the polarities thereof at any given instant, means connected to the output of said converting means for producing a plurality of constant frequency pulses the number of which is proportional to the widths of those portions of the aforesaid variable width square wave signal having the same polarity, and means effectively connected to said pulse producing means for timely sampling said pulses in terms of binary bits.

Claim 3

Means for producing random binomial numbers comprising in combination, means for producing a random frequency-random amplitude signal, a pulse generator having a pair of inputs one of which is coupled to the output of said random frequency-random amplitude signal producing means, an external pulse generator having an output connected to the other input of said pulse generator for timely initiating the pulses therefrom, a first And gate having a pair of inputs one of which is coupled to the output of said pulse generator for timely response to the pulse therefrom, a master clock having an output connected to the other input of said first And gate, a bistable multivibrator having a pair of inputs one of which is coupled to the output of said first And gate and the other of which is connected to the output of said master clock, a synchronous generator having a pair of inputs respectively connected to the outputs of said external pulse generator and the aforesaid master clock, a variable delay line coupled to the output of said synchronous generator, a second And gate having a trio of inputs one of which is connected to the output of said bistable multivibrator, another of which is connected to the output of said master clock, and the other of which is connected to the output of the aforesaid variable delay line.

Claim 4

Means for producing random binomial numbers comprising in combination, means for producing a random frequency-random amplitude signal, a pulse generator having a pair of inputs one of which is coupled to the output of said random frequency-random amplitude signal producing means, an external pulse generator having an output connected to the other input of said pulse generator for timely initiating the pulses therefrom, a first And gate having a pair of inputs one of which is coupled to the output of said pulse generator for timely response to the pulse therefrom, a master clock having an output connected to the other input of said first And gate, a bistable multivibrator having a pair of inputs one of which is coupled to the output of said first And gate and the other of which is connected to the output of said master clock, a synchronous generator having a pair of inputs respectively connected to the outputs of said external pulse generator and the aforesaid master clock, a variable delay line coupled to the output of said synchronous generator, a second And gate having a trio of inputs one of which is connected to the output of said bistable multivibrator, another of which is connected to the output of said master clock, and the other of which is connected to the output of the aforesaid variable delay line.

Claim 5

Means for producing random binomial numbers comprising in combination, a pulse generator, means coupled to the input of said pulse generator for modulating the pulses thereof in such manner that their leading edges occur at fixed intervals while their pulse widths are randomly varied between fixed limits, means connected to the output of said pulse modulating means for producing successive packets of pulses which have a constant frequency that is higher than the highest frequency of the pulses generated by the aforesaid pulse generator, each of said successive packets of pulses having a width substantially equal to the widths of those portions of said modulated pulses having a similar predetermined polarity, and means coupled to the output of said packet producing means for sampling each packet therefrom a predetermined time before the end pulse thereof is terminated in terms of a one or a zero is a pulse is or is not present respectively at the sampling instant.

Claim 6

Means for producing random binomial numbers comprising in combination, a pulse generator, means coupled to the input of said pulse generator for modulating the pulses thereof in such manner that their leading edges occur at fixed intervals while their pulse widths are randomly varied between fixed limits, means connected to the output of said pulse modulating means for producing successive packets of pulses which have a constant frequency that is higher than the highest frequency of the pulses generated by the aforesaid pulse generator, each of said successive packets of pulses having a width substantially equal to the widths of those portions of said modulated pulses having a similar predetermined polarity, and means coupled to the output of said packet producing means for sampling each packet therefrom a predetermined time before the end pulse thereof is terminated in terms of a one or a zero is a pulse is or is not present respectively at the sampling instant.

Claim 7

The device of claim 3 wherein said means coupled to the input of said pulse generator for modulating the pulses thereof in such manner that their leading edges occur at fixed intervals while their pulse widths are randomly varied between fixed limits comprise an external pulse generator.

Claim 8

The device of claim 3 wherein said means connected to the output of said pulse modulating means for producing successive packets of pulses which have a constant frequency that is higher than the highest frequency of the pulses generated by the aforesaid pulse generator comprises a master clock and an And gate having a pair of inputs one of which is connected to the output of said master clock and the other of which is coupled to the output of said pulse generator.

Claim 9

The device of claim 5 further characterized by a bistable multivibrator having a pair of inputs one of which is coupled to the output of said master clock and the other of which is connected to the output of the aforesaid And gate.

Claim 10

A random number generating means for producing a random sequence of binary ones and zeros with a predetermined probability of a one comprising in combination, means for producing a plurality of signals each of which contain a random sequence of ones and zeros, a first shift register having a plurality of stages equal in number to the number of said plurality of signals, said first shift register being connected to said producing means for respective storage of said plurality of signals in the stages thereof, a reference shift register having a plurality of stages of like number as said first shift register, means coupled to said shift registers for simultaneously shifting same in synchronization with the production of said random sequence of ones and zeros, and means connected to the outputs of both of said shift registers for comparing the total contents thereof between shifts and providing an outout therefrom in terms of a random sequence of binary ones and zeros having a predetermined probability of a one.

Claim 11

A random number generating means for producing a random sequence of binary ones and zeros with a predetermined probability of a one comprising in combination, means for producing a plurality of signals each of which contain a random sequence of ones and zeros, a first shift register having a plurality of stages equal in number to the number of said plurality of signals, said first shift register being connected to said producing means for respective storage of said plurality of signals in the stages thereof, a reference shift register having a plurality of stages of like number as said first shift register, means coupled to said shift registers for simultaneously shifting same in synchronization with the production of said random sequence of ones and zeros, and means connected to the outputs of both of said shift registers for comparing the total contents thereof between shifts and providing an outout therefrom in terms of a random sequence of binary ones and zeros having a predetermined probability of a one.

Claim 12

The invention according to claim 7 wherein said means for producing a plurality of signals each of which contain a random sequence of ones and zeros comprise a plurality of channels each of which include a thyratron noise generator, an amplifier coupled to the output of said thyratron noise generator, a pulse generator connected to the output of said amplifier, a first And gate connected to the output of said pulse generator and adapted for connection to a master clock, a bistable multivibrator coupled to the output of said first And gate and adapted for being connected to the output of said master clock, and a second And gate coupled to the output of said bistable multivibrator for passing the signal representing the zero or one state thereof in response to a pair of coincident signals adapted for being supplied to said second And gate by a synchronous generator driven variable delay line in accordance with a predetermined timing arrangement.

Claim 13

Means for producing random binomial numbers comprising in combination, a typical channel consisting of a thyratron noise generator, an amplifier coupled to the output of said thyratron noise generator, a pulse generator having a pair of inputs one of which is connected to the output of said pulse generator, a first And gate having a pair of inputs one of which is connected to the output of said pulse generator, a flip-flop having a pair of inputs one of which is connected to the output of said first And gate, a second And gate having first, second, and third inputs, the first of which is connected to the output of said flip-flop, a master clock having an output connected to the other inputs of said first And gate and said flip-flop and the second input of said second And gate, an external pulse generator having an output connected to the other input of said pulse generator, a synchronous generator connected to the outputs of said master clock and said external pulse generator, and a variable delay interconnecting the output of said synchronous generator and the third input of the aforesaid second And gate.

Claim 14

Means for producing random binomial numbers comprising in combination, a typical channel consisting of a thyratron noise generator, an amplifier coupled to the output of said thyratron noise generator, a pulse generator having a pair of inputs one of which is connected to the output of said pulse generator, a first And gate having a pair of inputs one of which is connected to the output of said pulse generator, a flip-flop having a pair of inputs one of which is connected to the output of said first And gate, a second And gate having first, second, and third inputs, the first of which is connected to the output of said flip-flop, a master clock having an output connected to the other inputs of said first And gate and said flip-flop and the second input of said second And gate, an external pulse generator having an output connected to the other input of said pulse generator, a synchronous generator connected to the outputs of said master clock and said external pulse generator, and a variable delay interconnecting the output of said synchronous generator and the third input of the aforesaid second And gate.

Claim 15

Means for producing random binomial numbers comprising in combination, a typical channel consisting of a thyratron noise generator, an amplifier coupled to the output of said thyratron noise generator, a pulse generator having a pair of inputs one of which is connected to the output of said amplifier, a first And gate having a pair of inputs one of which is connected to the output of said pulse generator, a flip-flop having a pair of inputs one of which is connected to the output of said first And gate, a second And gate having first, second, and third inputs, the first of which is connected to the output of said flip-flop, a master clock having an output connected to the other inputs of said first And gate and said flip-flop and the second input of said second And gate, an external pulse generator having an output connected to the other input of said pulse generator, a synchronous generator connected to the outputs of said master clock and said external pulse generator, and a variable delay interconnecting the output of said synchronous generator and the third input of the aforesaid second And gate, a shift register having a plurality of stages with one thereof connected to the output of said second And gate of the aforesaid typical channel, a plurality of additional channels similar to said typical channel respectively connected to the inputs of the remaining stages of said shift register and to the outputs of said master clock, external pulse generator, synchronous generator, and variable delay for timely actuation thereof, a reference shift register having a plurality of stages equal in number to the number of stages in the aforesaid shift register with a preset binomial program stored therein, a shift right generator interconnecting each of said shift registers and the output of said variable delay, means connected between the outputs of said master clock, said shift register, and said shift right generator for synchronizing the actuation thereof, and a comparator connected between the outputs of said shift register and the aforesaid reference shift register.

Claim 16

Means for producing random binomial numbers comprising in combination, a typical channel consisting of a thyratron noise generator, an amplifier coupled to the output of said thyratron noise generator, a pulse generator having a pair of inputs one of which is connected to the output of said amplifier, a first And gate having a pair of inputs one of which is connected to the output of said pulse generator, a flip-flop having a pair of inputs one of which is connected to the output of said first And gate, a second And gate having first, second, and third inputs, the first of which is connected to the output of said flip-flop, a master clock having an output connected to the other inputs of said first And gate and said flip-flop and the second input of said second And gate, an external pulse generator having an output connected to the other input of said pulse generator, a synchronous generator connected to the outputs of said master clock and said external pulse generator, and a variable delay interconnecting the output of said synchronous generator and the third input of the aforesaid second And gate, a shift register having a plurality of stages with one thereof connected to the output of said second And gate of the aforesaid typical channel, a plurality of additional channels similar to said typical channel respectively connected to the inputs of the remaining stages of said shift register and to the outputs of said master clock, external pulse generator, synchronous generator, and variable delay for timely actuation thereof, a reference shift register having a plurality of stages equal in number to the number of stages in the aforesaid shift register with a preset binomial program stored therein, a shift right generator interconnecting each of said shift registers and the output of said variable delay, means connected between the outputs of said master clock, said shift register, and said shift right generator for synchronizing the actuation thereof, and a comparator connected between the outputs of said shift register and the aforesaid reference shift register.

Claim 17

A generator for producing random binary bits comprising a typical channel including in combination, means for generating a random noise signal, means effectively connected to the output of said generating means for converting said random noise signal into a random width square wave having leading edges at fixed time intervals, means connected to the output of said converting means for producing a plurality of pulses the nummber of which is proportional to the widths of those portions of the aforesaid random width square wave having the same polarity, means effectively connected to said pulse producing means for timely sampling said pulses in terms of binary bits, a first shift register having a plurality of stages one of which is connected to the output of said sampling means for receiving and timely storing the binary bits therefrom, a plurality of additional channels each of which is identical to the aforesaid typical channel connected to the remaining stages of said first shift register respectively, a second shift register having a plurality of stages equal in number to the number of stages of said first shift register and having a predetermined binary bit program set therein, means connected to said first and second shift registers for timely shifting same, and means interconnecting the outputs of said first and second shift register for comparing the contents thereof in terms of a random sequence of binary bits with a predetermined probability that one type thereof predominates.

Claim 18

A generator for producing random binary bits comprising a typical channel including in combination, means for generating a random noise signal, means effectively connected to the output of said generating means for converting said random noise signal into a random width square wave having leading edges at fixed time intervals, means connected to the output of said converting means for producing a plurality of pulses the nummber of which is proportional to the widths of those portions of the aforesaid random width square wave having the same polarity, means effectively connected to said pulse producing means for timely sampling said pulses in terms of binary bits, a first shift register having a plurality of stages one of which is connected to the output of said sampling means for receiving and timely storing the binary bits therefrom, a plurality of additional channels each of which is identical to the aforesaid typical channel connected to the remaining stages of said first shift register respectively, a second shift register having a plurality of stages equal in number to the number of stages of said first shift register and having a predetermined binary bit program set therein, means connected to said first and second shift registers for timely shifting same, and means interconnecting the outputs of said first and second shift register for comparing the contents thereof in terms of a random sequence of binary bits with a predetermined probability that one type thereof predominates.