US4180203A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable test point selector circuit
Assignee: Westinghouse Electric Corp
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Filing: 1977-09-30
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Granted: 1979-12-25
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Expires: 1997-09-30
Abstract
Abstract A programmable test point selector circuit for interfacing a test set with a system to be tested is disclosed. Typically, the system to be tested is provided with a multi-pin connector or receptacle to which the automatic test set is connected. The disclosed programmable test point selector circuit is interposed between the test set and this connector. Digital program words from the test set are used to designate pins of the multi-pin connector for use as either an input pin or an output pin. Additionally, the programmable test point selector permits at least one voltage level of the digital signal supplied to any pin designated as an input to be independently programmed over a wide range of values. An output sensing circuit is also provided which permits any individual pin or group of pins to be selected for monitoring to determine the voltage level of the signal present at the selected output pin relative to a threshold level. The threshold level of the output sensing circuit is also programmable so that each output pin of the device being tested may be monitored for the correct level. Thus, the device under test can have a mixture of voltage levels on its output pins. The program to the programmable test point selector circuit is a series of digital signals supplied by the associated test system.
Inventors
- 👤 Harvey M. Masters
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:56
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31905; G01R31/31908; G01R31/31917; G01R31/31926
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
389 words
A programmed circuit for selectively coupling a multi-bit digital signal to a plurality of circuit nodes and for determining the status of signals present at said nodes; comprising: (a) a plurality of input circuits, each of said input circuits selecting which ones of said nodes the bits of said digital signal will be coupled to and generating a bit of said digital signal, each of said input circuit comprising a first plurality of two input AND gate circuits having their respective output terminals coupled to a plurality of voltage sources by a first plurality of resistors; (b) a first plurality of diodes each having first and second polarity terminals, said first plurality of diodes having their first polarity terminals connected in parallel and to one of said nodes, said second polarity terminal of each of said diodes being coupled to the output terminal of separate ones of said first plurality of two input AND gates; (c) a plurality of two input NAND gates each having its output coupled directly to said one and only one of said nodes; (d) a threshold detector circuit; (e) a second plurality of diodes each having first and second polarity terminals, said second plurality of diodes having their second like polarity terminals connected in parallel and to the input of said threshold detector; (f) a second plurality of resistors each having first and second terminals, each of said second plurality of resistors having its first terminal coupled to one and only one of said terminals of said first polarity of said second plurality of diodes, said second terminal of each of said second plurality of resistors being coupled to one and only one of said nodes; (g) a second plurality of two input AND gates, each of said second plurality of AND gates having its output terminal coupled to the junction formed by separate ones of said second plurality of diodes and said second plurality of resistors, with the inputs of said first and second plurality of AND gates and the input to said NAND gate coupled to receive a digital program signal which specifies to which ones of said circuit nodes the bits of said digital signal will be coupled and which one of said nodes will be coupled to the input of said detector to determine the status of the signal thereon.
Claim 2
Dependent Claim
389 words
A programmed circuit for selectively coupling a multi-bit digital signal to a plurality of circuit nodes and for determining the status of signals present at said nodes; comprising: (a) a plurality of input circuits, each of said input circuits selecting which ones of said nodes the bits of said digital signal will be coupled to and generating a bit of said digital signal, each of said input circuit comprising a first plurality of two input AND gate circuits having their respective output terminals coupled to a plurality of voltage sources by a first plurality of resistors; (b) a first plurality of diodes each having first and second polarity terminals, said first plurality of diodes having their first polarity terminals connected in parallel and to one of said nodes, said second polarity terminal of each of said diodes being coupled to the output terminal of separate ones of said first plurality of two input AND gates; (c) a plurality of two input NAND gates each having its output coupled directly to said one and only one of said nodes; (d) a threshold detector circuit; (e) a second plurality of diodes each having first and second polarity terminals, said second plurality of diodes having their second like polarity terminals connected in parallel and to the input of said threshold detector; (f) a second plurality of resistors each having first and second terminals, each of said second plurality of resistors having its first terminal coupled to one and only one of said terminals of said first polarity of said second plurality of diodes, said second terminal of each of said second plurality of resistors being coupled to one and only one of said nodes; (g) a second plurality of two input AND gates, each of said second plurality of AND gates having its output terminal coupled to the junction formed by separate ones of said second plurality of diodes and said second plurality of resistors, with the inputs of said first and second plurality of AND gates and the input to said NAND gate coupled to receive a digital program signal which specifies to which ones of said circuit nodes the bits of said digital signal will be coupled and which one of said nodes will be coupled to the input of said detector to determine the status of the signal thereon.
Claim 3
Dependent Claim
60 words
A circuit in accordance with claim 1 further including at least one resistor coupled between the input of said detector circuit and the output of a threshold gate circuit such that the impedance between the input changes to change the threshold of said detector circuit, depending on the logic state of a digital input signal to said theshold gate circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-12-24 | 1983-06-25 | 1983-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-12-24 | 1987-06-25 | 1987-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-12-24 | 1991-06-25 | 1991-12-25 | $7700.00 | Window Closed / Lapsed |