Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
120 words
A method for serially bit-switching digital word synchronized (word aligned) data between inputs and outputs of a digital switch comprising the steps of converting data from different incoming channels to said switch into a bit interleaved bitstream on a single data highway, bit switching said bitstream via a switch memory, determining those bits which incur a switch memory delay as opposed to those bits which do not incur a said delay, applying a said delay to said bits which do not incur said delay, and applying a said delay to a synchronization signal for synchronizing the word boundary of outgoing data from the switch relative to a synchronization signal for synchronizing the word boundary of incoming data to the switch.
Claim 2
Independent Claim
120 words
A method for serially bit-switching digital word synchronized (word aligned) data between inputs and outputs of a digital switch comprising the steps of converting data from different incoming channels to said switch into a bit interleaved bitstream on a single data highway, bit switching said bitstream via a switch memory, determining those bits which incur a switch memory delay as opposed to those bits which do not incur a said delay, applying a said delay to said bits which do not incur said delay, and applying a said delay to a synchronization signal for synchronizing the word boundary of outgoing data from the switch relative to a synchronization signal for synchronizing the word boundary of incoming data to the switch.
Claim 3
Dependent Claim
165 words
A switch for serially bit-switching digital word synchronized (word aligned) data between inputs and outputs of said switch, wherein said switch comprises circuit means for converting data from different incoming channels to said switch into a bit interleaved bitstream on a single data highway, a switch memory for receiving sequentially said data from said highway and bit switching said data to rearrange the order of data in said bitstream according to connections to be made through the switch, further circuit means for determining those bits through the switch which incur a switch memory cycle delay as opposed to those bits which do not incur a said delay, a delay equalizer circuit for applying a said delay to those bits which do not incur a switch memory cycle delay and a delay compensator circuit for delaying a synchronization signal for synchronizing the word boundary of outgoing data from the switch relative to a synchronization signal for synchronizing the word boundary of incoming data to the switch.
Claim 4
Dependent Claim
165 words
A switch for serially bit-switching digital word synchronized (word aligned) data between inputs and outputs of said switch, wherein said switch comprises circuit means for converting data from different incoming channels to said switch into a bit interleaved bitstream on a single data highway, a switch memory for receiving sequentially said data from said highway and bit switching said data to rearrange the order of data in said bitstream according to connections to be made through the switch, further circuit means for determining those bits through the switch which incur a switch memory cycle delay as opposed to those bits which do not incur a said delay, a delay equalizer circuit for applying a said delay to those bits which do not incur a switch memory cycle delay and a delay compensator circuit for delaying a synchronization signal for synchronizing the word boundary of outgoing data from the switch relative to a synchronization signal for synchronizing the word boundary of incoming data to the switch.
Claim 5
Dependent Claim
76 words
A switch according to claim 2, wherein said further circuit means comprises a comparator for comparing address information for sequentially and cyclically writing into said switch memory with address information for random reading from said switch memory and providing an output when said read address is equal to or less than said write address, the output of said comparator being provided to said delay equalizer circuit to cause said delay equalizer circuit to apply said delay.
Claim 6
Dependent Claim
114 words
A switch according to claim 3, wherein said delay equalizer circuit includes a random access memory (RAM) for sequentially receiving the rearranged data bits from said switch memory and cyclically writing the bits into successive locations thereof, said rearranged bits being cyclically read from said RAM so as to incur a said delay, said delay equalizer circuit also including a bypass connection whereby data from said switch memory is caused to bypass said RAM and an AND/OR gate arrangement to switch either the data bits from said RAM or from said bypass connection to the switch output depending respectively on whether said output of said comparator is present or not at said equalizer circuit.