Three state bus driver with protection circuitry

Claim 1

In a bus driver circuit of the kind having an input circuit for receiving an input logic signal, an output circuit including a push-pull field effect transistor pair for driving an output bus connected to a common junction of said transistor pair, each of said transistor pair having a gate, source, and drain, and means including at least one inverter stage coupled between said input circuit and said output circuit for translating said input logic signal from said input circuit to said output circuit and developing a three state logic output signal at said output bus, the improvement of means for limiting current flow through one of said transistors that is normally conducting when said output bus is short circuited from a normally HIGH logic level to a LOW logic level and for limiting current flow through the other one of said transistors that is normally conducting when said output bus is short circuited from a normally LOW logic level to a HIGH logic level, said current limiting means comprising: a first field effect transistor having a source to drain circuit connected in shunt between the gate and source of said one transistor, second and third field effect transistors connected in series with each other at a common junction and in parallel with the source to drain circuit of said other one transistor, and a fourth field effect transistor connected in shunt between the gate and source of said other one transistor, each of said first, second, third and fourth transistors having a gate, source, and drain, means coupling the gate of said fourth transistor to the common junction of said second and third transistors, said first transistor being normally non-conducting and rendered conducting to reduce the gate drive to said one transistor when said output bus is short circuited from a normally HIGH logic level to a LOW logic level, and said fourth transistor being normally non-conducting and rendered conducting to reduce the gate drive to said other one transistor when said output bus is short circuited from a normally LOW logic level to a HIGH logic level, said first and fourth transistors returning to their respective non-conducting states when the short circuits are removed, thereby to preserve the logic information present on said output bus before it was short circuited.