Clamp circuit for RGB output stages

Claim 2

In a television receiver having a plurality of signals AC coupled from the output of a chrominance demodulator to the inputs of respective chrominance amplifiers, a clamp circuit comprising: voltage dividing means coupled to a source of pulses characterized by an amplitude, A, and a pulsewidth, T, for dividing said pulses by a factor, K; a plurality of clamping diodes having common ends coupled to the output of the dividing means and other ends separately connected to respective inputs of the chrominance amplifiers and capacitively coupled to associated signal outputs of the chromminance demodulator; diode means having one end coupled to the output of the dividing means; and a bias supply characterized by an amplitude B and coupled to another end of the diode means whereby a clamping period is established, said clamping period having a duration less than T by a factor directly related to K and inversely related to the ratio of A to B.

Claim 3

A clamp circuit as defined in claim 1 wherein the dividing means comprises: a first resistance coupled between a source of flyback pulses and the common ends of the clamping diodes, and a second resistance coupled between the common ends of the clamping diodes and a reference potential.

Claim 4

A clamp circuit as defined in either claim 1 or claim 2 wherein the clamping diodes have anodes coupled to the output of the dividing means and cathodes separately connected to respective inputs of the chrominance amplifiers.

Claim 5

A clamp circuit as defined in claim 3 wherein the diode means has an anode coupled to the anodes of the clamping diodes and a cathode coupled to the bias supply so that the clamping diodes and diode means are rendered conductive during the clamping period.

Claim 6

A clamp circuit as defined in claim 1 wherein the dividing means is coupled to a source of horizontal flyback pulses so that the clamping period is less than the duration, T, of the flyback period by a factor approximately equal to: ##EQU3##

Claim 7

In a color television receiver having a first chromminance demodulator output coupled through a first capacitor to the input of the RED chrominance amplifier, a second demodulator output coupled through a second capacitor to the input of the GREEN chrominance amplifier, and a third demodulator output coupled through a third capacitor to the input of the BLUE chrominance amplifier, a clamp circuit comprising: voltage dividing means having an input coupled to a source of flyback pulses characterized by a period T and an amplitude A, said means for dividing those pulses by a factor K; first, second and third clamping diodes, each separately connected at one end to the inputs of the RED, GREEN and BLUE amplifiers respectively and commonly connected to the other end to each other and to an output of the voltage dividing means; a bias supply characterized by an amplitude B; a switch coupled between the output of the dividing means and the bias supply so that the switch is rendered conductive during the flyback period for a length of time that is less than T by a factor approximately equal to: ##EQU4##

Claim 8

In a color television receiver having a first chromminance demodulator output coupled through a first capacitor to the input of the RED chrominance amplifier, a second demodulator output coupled through a second capacitor to the input of the GREEN chrominance amplifier, and a third demodulator output coupled through a third capacitor to the input of the BLUE chrominance amplifier, a clamp circuit comprising: voltage dividing means having an input coupled to a source of flyback pulses characterized by a period T and an amplitude A, said means for dividing those pulses by a factor K; first, second and third clamping diodes, each separately connected at one end to the inputs of the RED, GREEN and BLUE amplifiers respectively and commonly connected to the other end to each other and to an output of the voltage dividing means; a bias supply characterized by an amplitude B; a switch coupled between the output of the dividing means and the bias supply so that the switch is rendered conductive during the flyback period for a length of time that is less than T by a factor approximately equal to: ##EQU4##

Claim 9

A clamp circuit as defined in claim 6 wherein the dividing means comprises: a first resistor coupled to the horizontal flyback winding, and a second resistor coupled between a junction formed by the first resistor and by the commonly connected ends of the clamping diodes and a reference potential.

Claim 10

A clamp circuit as defined in claim 7 wherein the switch comprises a diode having an anode connected to commonly connected anodes of the clamping diodes and a cathode coupled to the bias supply.

Claim 11

A clamp circuit as defined in claim 8 further comprising a capacitance coupled between the output of the voltage dividing means and the reference potential for delaying the pulses at the output of the dividing means.