Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
309 words
A speed-and-phase control circuit for a rotary machine, comprising: a. frequency divider means responsive to an input signal whose frequency is proportional to the revolution number of said rotary machine for providing frequency division of said input signal and for providing said frequency-divided input signal as a first output signal; b. logical circuit means responsive to said input signal and to said first output signal for providing in timed relationship a first timing pulse having a pulse width equal to a half period of said input signal, the rising edge of said first timing pulse being substantially coincident with the falling edge of said input signal, a second timing pulse having a pulse width equal to one period of said input signal, the rising edge of said second timing pulse being substantially coincident with the falling edge of said first timing pulse, and a third timing pulse having a pulse width equal to a half period of said input signal, the rising edge of said third timing pulse being substantially coincident with the falling edge of said second timing pulse; c. charging circuit means for charging a first capacitor circuit to a predetermined voltage level in response to said first timing pulse; d. discharge circuit means for discharging according to the constant current mode said first capacitor circuit in response to said second timing pulse; e. first gate circuit means for transferring said charge present on said first capacitor circuit to a second capacitor circuit in response to said second timing pulse; and f. second gate circuit means for transferring said charge present on said first capacitor circuit to a third capacitor circuit in response to a reference timing pulse having a reference phase, whereby the speed and phase of said rotary machine is selectively controlled in accordance with the voltages present on said second and third capacitor circuits.
Claim 2
Dependent Claim
309 words
A speed-and-phase control circuit for a rotary machine, comprising: a. frequency divider means responsive to an input signal whose frequency is proportional to the revolution number of said rotary machine for providing frequency division of said input signal and for providing said frequency-divided input signal as a first output signal; b. logical circuit means responsive to said input signal and to said first output signal for providing in timed relationship a first timing pulse having a pulse width equal to a half period of said input signal, the rising edge of said first timing pulse being substantially coincident with the falling edge of said input signal, a second timing pulse having a pulse width equal to one period of said input signal, the rising edge of said second timing pulse being substantially coincident with the falling edge of said first timing pulse, and a third timing pulse having a pulse width equal to a half period of said input signal, the rising edge of said third timing pulse being substantially coincident with the falling edge of said second timing pulse; c. charging circuit means for charging a first capacitor circuit to a predetermined voltage level in response to said first timing pulse; d. discharge circuit means for discharging according to the constant current mode said first capacitor circuit in response to said second timing pulse; e. first gate circuit means for transferring said charge present on said first capacitor circuit to a second capacitor circuit in response to said second timing pulse; and f. second gate circuit means for transferring said charge present on said first capacitor circuit to a third capacitor circuit in response to a reference timing pulse having a reference phase, whereby the speed and phase of said rotary machine is selectively controlled in accordance with the voltages present on said second and third capacitor circuits.
Claim 3
Dependent Claim
119 words
The speed-and-phase control circuit for a rotary machine as recited in claim 1, further comprising, first buffer circuit means responsive to said voltage present on said second capacitor circuit for providing said voltage as a second output signal, said first buffer circuit means exhibiting a high input impedance, second buffer circuit means responsive to said voltage present on said third capacitor circuit for providing said voltage as a third output signal, said second buffer circuit means exhibiting a high input impedance, and driving circuit means responsive to said second and third output signals for providing a speed-and-phase control signal to said rotary machine derived in accordance with the difference between said second output signal and said third output signal.
Claim 4
Dependent Claim
77 words
The speed-and-phase control circuit for a rotary machine as recited in claim 1, wherein said logical circuit means includes first means for producing the logical product of the inverse of said input signal and the inverse of said first output signal, said logical product being said first timing pulse, and second means for producing the logical product of said input signal and the inverse of said first output signal, said logical product being said third timing pulse.
Claim 5
Dependent Claim
78 words
The speed-and-phase control circuit for a rotary machine as recited in claim 3, wherein said first means includes a first inverter having an input responsive to said input signal, a second inverter having an input responsive to said first output signal, and an AND circuit having a first input responsive to the output of said first inverter, a second input response to the output of said second inverter and an output, said output being said first timing pulse.
Claim 6
Dependent Claim
64 words
The speed-and-phase control circuit for a rotary machine as recited in claim 3, wherein said second means include a third inverter having an input responsive to said first output signal and an AND circuit having a first input responsive to the output of said third inverter, a second input responsive to said input signal and an output, said output being said third timing pulse.