US4173003A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Deltic (time compressor) with adjustable multiplication ratio
Assignee: United States Department of the Navy
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Filing: 1970-12-28
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Granted: 1979-10-30
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Expires: 1990-12-28
Abstract
Abstract A delay line time compressor which can be operated at different multiplicon factors by virtue of changes in the length of the recirculation loop for selected parts of the recirculation routine. A preferred embodiment utilizes an organization of parallel recirculation loops and is well adapted to semiconductor shift register implementation. Another embodiment utilizes a single high frequency delay element such as glass, in combination with a shift register.
Inventors
- 👤 Fred W. Thies
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:21
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/66; H04B1/662; G; G01; G01R; G01R23/00; G01R23/16; G01R23/175; H03; H03H; H03H17/00; H03H17/0009
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
219 words
In a deltic device comprising in combination data recirculation loop means, means for feeding data signals into said loop means, and a source of control signals for controlling input, recirculation, and output of data signals; first time delay means forming part of said recirculation loop means and having a first predetermined delay length; second time delay means having a second predetermined delay length; switching means connected to said first and second delay means and responsive to said control signals to connect said second delay means into and out of series relation with said first delay means in said recirculation loop means so as to provide long recirculation loop means for a first predetermined number of recirculations and shorter recirculation loop means for a second predetermined number of recirculations; said recirculation loop means comprising a plurality of recirculation loops, k in number; said first delay means comprising an N/k bit shift register for each of said loops, where N is the total bit capacity of said first delay means; said second delay means comprising a single bit register for each of said loops; and said switching means comprising individual switching means for each of said loops and responsive to said control signals to connect the respective single bit registers into and out of series relation with the corresponding shift registers.
Claim 2
Dependent Claim
219 words
In a deltic device comprising in combination data recirculation loop means, means for feeding data signals into said loop means, and a source of control signals for controlling input, recirculation, and output of data signals; first time delay means forming part of said recirculation loop means and having a first predetermined delay length; second time delay means having a second predetermined delay length; switching means connected to said first and second delay means and responsive to said control signals to connect said second delay means into and out of series relation with said first delay means in said recirculation loop means so as to provide long recirculation loop means for a first predetermined number of recirculations and shorter recirculation loop means for a second predetermined number of recirculations; said recirculation loop means comprising a plurality of recirculation loops, k in number; said first delay means comprising an N/k bit shift register for each of said loops, where N is the total bit capacity of said first delay means; said second delay means comprising a single bit register for each of said loops; and said switching means comprising individual switching means for each of said loops and responsive to said control signals to connect the respective single bit registers into and out of series relation with the corresponding shift registers.
Claim 3
Dependent Claim
59 words
In a deltic combination according to claim 1: said source of control signals comprising oscillator means; a plurality of frequency divider means connected to said oscillator means and operative to provide a plurality of control signals of predetermined frequency and time relation; and switch means for selectively deriving said control signals from different ones of said frequency divider means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-10-29 | 1983-04-30 | 1983-10-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-10-29 | 1987-04-30 | 1987-10-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-10-29 | 1991-04-30 | 1991-10-30 | $7700.00 | Window Closed / Lapsed |