US4172262A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Line sampling circuit for television receiver
Assignee: Sanyo Electric Co Ltd
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Filing: 1978-05-09
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Granted: 1979-10-23
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Expires: 1998-05-09
Abstract
Abstract A composite synchronizing signal during a vertical blanking interval includes horizontal sync pulses, equalizing pulses and vertical sync pulses. A line sampling circuit includes a vertical pulse gate which detects and filters an even number of vertical sync pulses, a flyback pulse gate which filters the flyback pulses sequentially after the vertical pulse gate has filtered the even number of vertical sync pulses, and a 5-bit binary counter which counts the even number of vertical sync pulses and the flyback pulses. The line sampling circuit further includes a line decoder which produces a signal after the 5-bit binary counter has counted the even number of vertical sync pulses and a predetermined number of flyback pulses for sampling a particular line defined between the neighboring horizontal sync pulses produced during the vertical blanking interval.
Inventors
- 👤 Nobukazo Hosoya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:10
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/08; H04N5/10; H04N7/00; H04N7/08; H04N7/087
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
253 words
In a television receiver set having means for separating and generating a composite sync pulse, which include equalizing pulses, vertical sync pulses and horizontal sync pulses and means for generating horizontal frequency pulses, a line sampling circuit for detecting a particular line defined between the neighboring horizontal sync pulses produced during the vertical blanking interval and carrying a reference signal on said particular line and producing a signal indicative of the presence of said particular line, said line sampling circuit comprising, in combination: first filtering means for filtering the vertical sync pulses; second filtering means for filtering the horizontal frequency pulses; means for counting said filtered vertical sync pulses and said filtered horizontal frequency pulses; gate means connected to the first and second filtering means and to the counting means for enabling said first filtering means to filter an even number of vertical sync pulses through the first filtering means and disabling said second filtering means to filter the horizontal frequency pulses therethrough when the first filtering means supplies the even number of vertical sync pulses, said gate means, after the first filtering means has filtered the even number of the vertical sync pulses, disabling said first filtering means to filter the vertical sync pulses and enabling said second filtering means to filter the horizontal frequency pulses, and line decoder means connected to the counter means for producing, after said counting means has counted a predetermined number of pulses, a pulsating signal having a pulse duration equal to one line horizontal scanning period.
Claim 2
Dependent Claim
253 words
In a television receiver set having means for separating and generating a composite sync pulse, which include equalizing pulses, vertical sync pulses and horizontal sync pulses and means for generating horizontal frequency pulses, a line sampling circuit for detecting a particular line defined between the neighboring horizontal sync pulses produced during the vertical blanking interval and carrying a reference signal on said particular line and producing a signal indicative of the presence of said particular line, said line sampling circuit comprising, in combination: first filtering means for filtering the vertical sync pulses; second filtering means for filtering the horizontal frequency pulses; means for counting said filtered vertical sync pulses and said filtered horizontal frequency pulses; gate means connected to the first and second filtering means and to the counting means for enabling said first filtering means to filter an even number of vertical sync pulses through the first filtering means and disabling said second filtering means to filter the horizontal frequency pulses therethrough when the first filtering means supplies the even number of vertical sync pulses, said gate means, after the first filtering means has filtered the even number of the vertical sync pulses, disabling said first filtering means to filter the vertical sync pulses and enabling said second filtering means to filter the horizontal frequency pulses, and line decoder means connected to the counter means for producing, after said counting means has counted a predetermined number of pulses, a pulsating signal having a pulse duration equal to one line horizontal scanning period.
Claim 3
Dependent Claim
111 words
A line sampling circuit as claimed in claim 1, further comprising reset means connected to the counting means and the gate means for producing a reset signal after the counting means has counted a certain number of pulses which is greater than said predetermined number of pulses, said reset signal being applied to the counting means for resetting said counting means and also to the gate means for resetting the first and second filtering means to disable further filtering of the horizontal frequency pulses through the second filtering means and to enable the first filtering means to filter the vertical sync pulses in the next succeeding field of the televised image.
Claim 4
Dependent Claim
15 words
A line sampling circuit as claimed in claim 1, wherein said even number is two.
Claim 5
Dependent Claim
121 words
A line sampling circuit as claimed in claim 1, wherein said first filtering means comprises a first transistor receiving said composite sync pulses, a capacitor connected to the first transistor, a source of electric power coupled to the capacitor for charging the capacitor during the presence of any one of pulses in said composite sync pulses and for discharging the capacitor during the absence of such any one of pulses in said composite sync pulses, said capacitor charging a voltage which is of the highest value during the presence of each of the vertical sync pulses, and a differential amplifier connected to said capacitor for detecting said highest voltage and producing a pulsating signal indicative of detection of said highest voltage.
Claim 6
Dependent Claim
36 words
A line sampling circuit as claimed in claim 4, further comprising a second transistor receiving said horizontal frequency pulses and connected to the capacitor for discharging said capacitor during the presence of said horizontal frequency pulese.
Claim 7
Dependent Claim
19 words
A line sampling circuit as claimed in claim 1, wherein said counting means comprises five sets of flip-flop circuits.
Claim 8
Dependent Claim
160 words
A line sampling circuit as claimed in claim 6, wherein each of said flip-flop circuit comprises a primary flip-flop constituted by first and second transistors, a steering flip-flop constituted by third and fourth transistors, two driving transistors and two adjusting resistors, said first transistor of the primary flip-flop having a collector-emitter path connected in parallel to one of the adjusting resistors and in series with a collector-emitter path of the third transistor of the steering flip-flop, said second transistor of the primary flip-flop having a collector-emitter path connected in parallel to the other of the adjusting resistor and in series with a collector-emitter path of the fourth transistor of the steering flip-flop, said third transistor of the steering flip-flop having a collector-emitter connected in parallel to a collector-emitter path of one of the driving transistors, and said fourth transistor of the steering flip-flop having a collector-emitter connected in parallel to a collector-emitter path of the other of the driving transistors.
Claim 9
Dependent Claim
107 words
A line sampling circuit as claimed in claim 2, wherein said reset means includes a reset pulse generating means comprising a charging transistor, a delay capacitor connected in series with a collector-emitter path of the charging transistor, a pulse generating transistor having a base thereof connected to one side of said delay capacitor and a source of electric power soupled to said charging transistor and to said pulse generating transistor, said delay capacitor charging a voltage upon application of pulse to said charging transistor and discharging the voltage through a base-emitter path of the pulse generating transistor for generating a sawtooth pulse from said pulse generating transistor.
Claim 10
Dependent Claim
107 words
A line sampling circuit as claimed in claim 2, wherein said reset means includes a reset pulse generating means comprising a discharging transistor, a delay capacitor connected in series with a collector-emitter path of the discharging transistor, a pulse generating transistor having a base thereof connected to one side of said delay capacitor and a source of electric power coupled to said discharging transistor and to said pulse generating transistor, said delay capacitor discharging a voltage upon application of pulse to said discharging transistor and charging the voltage through a base-emitter path of the pulse generating transistor for generating a sawtooth pulse from said pulse generating transistor.
Claim 11
Dependent Claim
19 words
A line sampling circuit as claimed in claim 1, wherein said counting means is constituted by a non-synchronizing counter.
Claim 12
Dependent Claim
60 words
A line sampling circuit as claimed in claim 10, wherein said line decoder means comprises a multi-emitter transistor having a plurality of emitters which are connected to the counting means and a controlling transistor receiving the horizontal frequency pulses and connected to the multi-emitter transistor, said controlling transistor actuating the multi-emitter transistor during the presence of the horizontal frequency pulses.
Claim 13
Dependent Claim
20 words
A line sampling circuit as claimed in claim 4, wherein said differential amplifier is constituted by a pair of transistors.
References Cited (Backward Citations)
US4089025A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-10-22 | 1983-04-23 | 1983-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-10-22 | 1987-04-23 | 1987-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-10-22 | 1991-04-23 | 1991-10-23 | $7700.00 | Window Closed / Lapsed |