Logic gate utilizing charge transfer devices

Claim 2

A logic gate, comprising: (a) a first storage gate capable of receiving a first and a second charge packet, each containing a predetermined quantity of charge Q representative of a binary bit; (b) a first transfer gate coupled to said first storage gate for allowing the transfer therethrough of charge at said first storage gate in excess of the quantity Q; (c) a charge sensing element having a master gate and a slave gate, said master gate being responsive to the excess of charge above said quantity Q that is transferred by said first transfer gate, said slave gate being directly connected to said master gate and acting as a transfer gate for charge transfer if, and only if, no charge is present at said master gate, and acting as a barrier gate for charge transfer if, and only if, charge is present at said master gate; (d) a control gate coupling said first storage gate to said slave gate, said control gate having a barrier state for inhibiting the transfer of charge from said first storage gate to said slave gate during the time interval required for charge from said first storage gate to reside at said master gate, said control gate also having a transfer state for the transfer of charge after the expiration of said time interval, and (e) means coupled to at least one of said slave and master gates for utilizing the individual charge packets Q that are present at said slave and master gates.

Claim 3

The invention according to claim 1 and further including means for applying a voltage of such magnitude to said control gate for inhibiting the transfer of charge from said storage gate to said slave gate during the time interval specified in (d), and means for changing the voltage on said control gate to a different magnitude for permitting the transfer of charge from said storage gate to said slave gate after the expiration of said time interval.

Claim 4

A logic gate as recited in claim 1 wherein said charge sensing element is of the non destructive type.

Claim 5

A TWO INPUT ADDER, comprising: (a) a first storage gate for receiving two charge packets representing digital bits each containing a predetermined quantity of charge Q; (b) a first transfer gate coupled to said first storage gate for allowing the transfer therethrough of charge in said first storage gate in excess of the quantity Q; (c) a non-destructive charge sensing element having a master gate for receiving and storing the excess of charge above said quantity Q that is transferred by said first transfer gate from said first storage gate, said charge sensing element also having a slave gate which is directly connected to said master gate and which acts as a transfer gate for charge transfer if, and only if, no charge is stored in said master gate, and which acts as a barrier gate for charge transfer if, and only if, charge is stored in said master gate; (d) a control gate coupling said first storage gate to said slave gate, said control gave having a barrier state for inhibiting the transfer of charge from said first storage gate to said slave gate during the time interval required for charge from said first storage gate to reside at said master gate, said control gave also having a transfer state for the transfer of charge after the expiration of said time interval, and (e) means for utilizing the charge packet that is present at said slave gate to provide a first signal which represents the least significant bit of the sum, and means for utilizing the charge packet that is present at said master gate to provide a second signal which represents the most significant bit of the sum.

Claim 6

A TWO INPUT ADDER, comprising: (a) a first storage gate for receiving two charge packets representing digital bits each containing a predetermined quantity of charge Q; (b) a first transfer gate coupled to said first storage gate for allowing the transfer therethrough of charge in said first storage gate in excess of the quantity Q; (c) a non-destructive charge sensing element having a master gate for receiving and storing the excess of charge above said quantity Q that is transferred by said first transfer gate from said first storage gate, said charge sensing element also having a slave gate which is directly connected to said master gate and which acts as a transfer gate for charge transfer if, and only if, no charge is stored in said master gate, and which acts as a barrier gate for charge transfer if, and only if, charge is stored in said master gate; (d) a control gate coupling said first storage gate to said slave gate, said control gave having a barrier state for inhibiting the transfer of charge from said first storage gate to said slave gate during the time interval required for charge from said first storage gate to reside at said master gate, said control gave also having a transfer state for the transfer of charge after the expiration of said time interval, and (e) means for utilizing the charge packet that is present at said slave gate to provide a first signal which represents the least significant bit of the sum, and means for utilizing the charge packet that is present at said master gate to provide a second signal which represents the most significant bit of the sum.

Claim 7

The invention according to claim 4 wherein the means in (e) includes first and second output storage gates coupled to said slave gate and said master gate, respectively, for receiving the charge packets, if any, residing at said slave gate and master gate.

Claim 8

The invention according to claim 5 and further including means for applying a first voltage to the output gate that is coupled to said slave gate to transfer charge representing the least significant bit, and means for subsequently applying a second voltage to the output gate that is coupled to said master gate to transfer charge representing the most significant bit.

Claim 9

A THREE INPUT ADDER, comprising: (a) a first storage gate for receiving three charge packets representing three binary digital bits each containing a predetermined quantity of charge Q; (b) a first transfer gate coupled to said first storage gate for allowing the transfer therethrough of charge in said first storage gate in excess of the quantity Q; (c) a non-destructive charge sensing element having a master gate for receiving and storing the excess of charge above said quantity Q that is transferred by said first transfer gate from said first storage gate, said charge sensing element also having a slave gate which is directly connected to said master gate and which acts as a transfer gate for charge transfer if, and only if, no charge is stored in said master gate, and which acts as a barrier gate for charge transfer if, and only if, charge is stored in said master gate; (d) a control gate coupling said first storage gate to said slave gate, said control gate having a barrier state for inhibiting the transfer of charge from said first storage gate to said slave gate during the time interval required for charge from said first storage gate to reside at said master gate, said control gate also having a transfer state for the transfer of charge after the expiration of said time interval; (e) a second transfer gate coupled to said master gate for allowing the transfer therethrough of charge in said master gate in excess of the quantity Q; (f) an intermediate storage gate coupled to said second transfer gate for receiving and storing the excess of charge above said quantity Q that is transferred by said second transfer gate from said master gate; (g) a third transfer gate coupled to said intermediate storage gate for allowing all charge stored in the intermediate storage gate to be transferred therethrough; (h) a sum gate coupled to both said third transfer gate and said slave gate for receiving charge of said quantity Q that is transferred from said third transfer gate and said slave gate; and (i) means for utilizing the charge that is present at the sum gate to provide a first signal which represents the least significant bit of the sum, and means for utilizing the charge that is present at said master gate to provide a second signal which represents the most significant bit of the sum.

Claim 10

A THREE INPUT ADDER, comprising: (a) a first storage gate for receiving three charge packets representing three binary digital bits each containing a predetermined quantity of charge Q; (b) a first transfer gate coupled to said first storage gate for allowing the transfer therethrough of charge in said first storage gate in excess of the quantity Q; (c) a non-destructive charge sensing element having a master gate for receiving and storing the excess of charge above said quantity Q that is transferred by said first transfer gate from said first storage gate, said charge sensing element also having a slave gate which is directly connected to said master gate and which acts as a transfer gate for charge transfer if, and only if, no charge is stored in said master gate, and which acts as a barrier gate for charge transfer if, and only if, charge is stored in said master gate; (d) a control gate coupling said first storage gate to said slave gate, said control gate having a barrier state for inhibiting the transfer of charge from said first storage gate to said slave gate during the time interval required for charge from said first storage gate to reside at said master gate, said control gate also having a transfer state for the transfer of charge after the expiration of said time interval; (e) a second transfer gate coupled to said master gate for allowing the transfer therethrough of charge in said master gate in excess of the quantity Q; (f) an intermediate storage gate coupled to said second transfer gate for receiving and storing the excess of charge above said quantity Q that is transferred by said second transfer gate from said master gate; (g) a third transfer gate coupled to said intermediate storage gate for allowing all charge stored in the intermediate storage gate to be transferred therethrough; (h) a sum gate coupled to both said third transfer gate and said slave gate for receiving charge of said quantity Q that is transferred from said third transfer gate and said slave gate; and (i) means for utilizing the charge that is present at the sum gate to provide a first signal which represents the least significant bit of the sum, and means for utilizing the charge that is present at said master gate to provide a second signal which represents the most significant bit of the sum.