US4168540A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Register building block with series connected cells to save dissipation loss
Assignee: Siemens AG
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Filing: 1978-08-28
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Granted: 1979-09-18
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Expires: 1998-08-28
Abstract
Abstract A register building block is disclosed comprising binary memory cells of cross-coupled double emitter transistors which are fed from a source of constant current and addressed by raising the collector potential. Given a predetermined operating voltage, two memory cells are connected in series to save dissipation loss in each constant current circuit. A switch controlled by one bit of the address is used to select one memory cell from the addressed pair of memory cells. The circuit arrangement disclosed is utilized in highly integrated building blocks.
Inventors
- 👤 Klaus Delker
- 👤 Wilhelm Wilhelm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 07:48
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4116; G11C11/413; G11C11/414; G11C11/415
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
124 words
A register building block, comprising: (a) a double memory cell member comprising two series-connected bipolar memory cells; (b) each bipolar memory cell comprising two double emitter transistors each having an ohmic collector-connected load resistance, bases and collectors of the two transistors being cross-coupled, a first emitter of each transistor being commonly connected to a constant current source and a second emitter of each transistor being connected to a bit line; (c) address means connected for elevating a potential of the load resistances of the double memory cell member to address a double memory cell member; and (d) switch means controlled by a bit of an address to select one of the bipolar memory cells of a double memory cell member selected by the address.
Claim 2
Dependent Claim
124 words
A register building block, comprising: (a) a double memory cell member comprising two series-connected bipolar memory cells; (b) each bipolar memory cell comprising two double emitter transistors each having an ohmic collector-connected load resistance, bases and collectors of the two transistors being cross-coupled, a first emitter of each transistor being commonly connected to a constant current source and a second emitter of each transistor being connected to a bit line; (c) address means connected for elevating a potential of the load resistances of the double memory cell member to address a double memory cell member; and (d) switch means controlled by a bit of an address to select one of the bipolar memory cells of a double memory cell member selected by the address.
Claim 3
Dependent Claim
25 words
The register building block of claim 1 in which for each one of simultaneously addressed double memory cell members a write-read control circuit is provided.
Claim 4
Dependent Claim
24 words
The register building block of claim 1 in which for all simultaneously addressed double memory cell members a common write-read control system is provided.
Claim 5
Dependent Claim
227 words
A memory system comprising: (a) a plurality of double memory cell members comprising first and second bipolar memory cells; (b) each memory cell comprising first and second double emitter transistors, a collector of each transistor connecting to an ohmic load, a base of the first transistor connecting to a collector of the second transistor and a collector of the first transistor connecting to a base of the second transistor, first emitters of the first and second transistors of the first memory cell being commonly connected to the ohmic loads of the second memory cell, first emitters of the first and second transistors of the second memory cell being commonly connected to a constant current source, second emitters of the first and second transistors of the first and second memory cells connecting to bit lines, the ohmic loads of the first and second transistors of the first memory cell connecting to selector lines of an address decoder; (c) switch means connecting to the bit lines for selecting one of the first and second memory cells of an addressed double memory cell member, said switch means being controlled by a bit of an address fed to the address decoder for addressing a double memory cell member; and (d) a write-read circuit means connected to the bit lines for writing and reading data from an address double memory cell member.
Claim 6
Dependent Claim
227 words
A memory system comprising: (a) a plurality of double memory cell members comprising first and second bipolar memory cells; (b) each memory cell comprising first and second double emitter transistors, a collector of each transistor connecting to an ohmic load, a base of the first transistor connecting to a collector of the second transistor and a collector of the first transistor connecting to a base of the second transistor, first emitters of the first and second transistors of the first memory cell being commonly connected to the ohmic loads of the second memory cell, first emitters of the first and second transistors of the second memory cell being commonly connected to a constant current source, second emitters of the first and second transistors of the first and second memory cells connecting to bit lines, the ohmic loads of the first and second transistors of the first memory cell connecting to selector lines of an address decoder; (c) switch means connecting to the bit lines for selecting one of the first and second memory cells of an addressed double memory cell member, said switch means being controlled by a bit of an address fed to the address decoder for addressing a double memory cell member; and (d) a write-read circuit means connected to the bit lines for writing and reading data from an address double memory cell member.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-09-17 | 1983-03-19 | 1983-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-09-17 | 1987-03-19 | 1987-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-09-17 | 1991-03-19 | 1991-09-18 | $7700.00 | Window Closed / Lapsed |