MIS capacitance element

Claim 2

A capacitance element formed in a complementary metal-insulator-semiconductor (MIS) device comprising: a semiconductor substrate of a first conductivity type; a well region formed in one principal surface of said semiconductor substrate, and having a second conductivity type opposite to that of said substrate; an insulator layer having a predetermined thickness and disposed on the surface of said well region; an electrically conductive layer of doped polycrystalline silicon having a predetermined area and disposed on said insulator layer; said well region and said conductive layer of polycrystalline silicon serving as opposite polar electrodes of the capacitance element; a dc voltage being applied between said electrodes with such polarity to prevent generation of an inversion layer in the surface of said well region; and means for electrically connecting said well region to said semiconductor substrate.

Claim 3

The capacitance element according to claim 1, wherein said semiconductor substrate is formed of silicon.

Claim 4

The capacitance element according to claim 2, wherein said insulator layer is formed by the same insulator film as the gate insulator of the MIS device, and said polycrystalline silicon layer is covered with a protective oxide layer.

Claim 5

The capacitance element according to claim 3, wherein said insulator layer is formed of one selected from the group consisting of silicon oxide, silicon nitride and the combination thereof.

Claim 6

A capacitance element formed in a complementary metal-insulator-semiconductor (MIS) device comprising: a semiconductor substrate of a first conductivity type; a well region formed in one principal surface of said semiconductor substrate, and having a second conductivity type opposite to that of said substrate; an insulator layer having a predetermined thickness and disposed on the surface of said well region; an electrically conductive layer of doped polycrystalline silicon having a predetermined area and disposed on said insulator layer; said well region and said conductive layer of polycrystalline silicon serving as opposite polar electrodes of the capacitance element; a dc voltage being applied between said electrodes with such polarity to prevent the generation of a voltage-dependent conductive channel in the surface of said well region, a first semiconductor region of high impurity concentration of said second conductivity type formed in at least a peripheral part of said well region in contact with said semiconductor substrate, a second semiconductor region of high impurity concentration of said first conductivity type formed in a part of said first semiconductor region in contact with said semiconductor substrate, and means for electrically connecting said first semiconductor region to said semiconductor substrate through said second semiconductor region.

Claim 7

A capacitance element formed in a complementary metal-insulator-semiconductor (MIS) device comprising: a semiconductor substrate of a first conductivity type; a well region formed in one principal surface of said semiconductor substrate, and having a second conductivity type opposite to that of said substrate; an insulator layer having a predetermined thickness and disposed on the surface of said well region; an electrically conductive layer of doped polycrystalline silicon having a predetermined area and disposed on said insulator layer; said well region and said conductive layer of polycrystalline silicon serving as opposite polar electrodes of the capacitance element; a dc voltage being applied between said electrodes with such polarity to prevent the generation of a voltage-dependent conductive channel in the surface of said well region, a first semiconductor region of high impurity concentration of said second conductivity type formed in at least a peripheral part of said well region in contact with said semiconductor substrate, a second semiconductor region of high impurity concentration of said first conductivity type formed in a part of said first semiconductor region in contact with said semiconductor substrate, and means for electrically connecting said first semiconductor region to said semiconductor substrate through said second semiconductor region.

Claim 8

The capacitance element according to claim 5, wherein said first semiconductor region is formed in contact with a portion of the outer periphery of said insulator layer.

Claim 9

The capacitance element according to claim 5, wherein said conductive layer is covered with a protective insulator layer through which an electrode is extracted for applying said dc voltage.

Claim 10

The capacitance element according to claim 7, wherein said electrode comprises a metal layer disposed on the surface of said protective insulator layer with a part of said metal layer extending to said electrically conductive layer through a through-hole provided in said protective insulator layer.

Claim 11

The capacitance element according to claim 7, wherein another electrode is formed of a metal layer extending from the surface of said first semiconductor region of high impurity concentration of said second conductivity type formed in said at least a peripheral part of said well region in contact with said semiconductor substrate, said metal layer covering said protective insulator layer overlying said conductive layer to increase capacitance.

Claim 12

The capacitance element according to claim 9, wherein said first semiconductor region has a ring-like shape surrounding a main surface area of said well region beneath said insulator layer.

Claim 13

The capacitance element according to claim 9, wherein said first semiconductor region includes a plurality of bar-shaped regions spaced from each other, and said insulator layer covers the surface of said well region between said bar-shaped regions.

Claim 14

The capacitance element according to claim 5, wherein said semiconductor substrate is formed of silicon, and said insulator layer is formed of silicon oxide.

Claim 15

The capacitance element according to claim 5, wherein said semiconductor substrate is formed of silicon, and said insulator layer is formed of silicon nitride.

Claim 16

The capacitance element according to claim 5, wherein said insulator layer is a double layer consisting of a silicon oxide layer and a silicon nitride layer.

Claim 17

In a semiconductor integrated circuit device comprising a semiconductor substrate of a first conductivity type, a complementary metal-insulator-semiconductor (MIS) device including a metal-insulator-semiconductor field-effect transistor (MISFET) of a first conductivity channel type formed in one surface of said substrate and a MISFET of a second conductivity channel type formed in the surface of a first well region in the substrate and having a second conductivity type opposite to that of said substrate, and a semiconductor capacitance element formed in the surface of said semiconductor substrate, said semiconductor capitance element comprising: a second well region formed in said semiconductor substrate at the same time with said first well region, and having the same conductivity type as that of said first well region; a gate insulator layer having a predetermined thickness and disposed on the surface of said second well region;

Claim 18

In a semiconductor integrated circuit device comprising a semiconductor substrate of a first conductivity type, a complementary metal-insulator-semiconductor (MIS) device including a metal-insulator-semiconductor field-effect transistor (MISFET) of a first conductivity channel type formed in one surface of said substrate and a MISFET of a second conductivity channel type formed in the surface of a first well region in the substrate and having a second conductivity type opposite to that of said substrate, and a semiconductor capacitance element formed in the surface of said semiconductor substrate, said semiconductor capitance element comprising: a second well region formed in said semiconductor substrate at the same time with said first well region, and having the same conductivity type as that of said first well region; a gate insulator layer having a predetermined thickness and disposed on the surface of said second well region;

Claim 19

an electrically conductive layer having a predetermined area and disposed on said insulator layer; said second well region and said conductive layer serving respectively as opposite polar electrodes of the semiconductor capacitance element; and means for electrically connecting said second well region to said semiconductor substrate, wherein said opposite polar electrodes have a dc voltage applied therebetween with a polarity for preventing generation of a voltage-dependent conductive channel in the surface of said second well region.

Claim 20

an electrically conductive layer having a predetermined area and disposed on said insulator layer; said second well region and said conductive layer serving respectively as opposite polar electrodes of the semiconductor capacitance element; and means for electrically connecting said second well region to said semiconductor substrate, wherein said opposite polar electrodes have a dc voltage applied therebetween with a polarity for preventing generation of a voltage-dependent conductive channel in the surface of said second well region.

Claim 21

The capacitance element according to claim 15, wherein said semiconductor substrate is formed of silicon.

Claim 22

The capacitance element according to claim 16, wherein said gate insulator layer is formed of the same insulator film as the gate insulator film of said MISFETs, and said conductive layer is covered with a protective oxide layer.

Claim 23

The capacitance element according to claim 17, wherein said semiconductor is silicon, and said gate insulator layer is formed of one selected from the group consisting of silicon oxide, silicon nitride and the combination thereof.

Claim 24

The capacitance element according to claim 16, wherein said conductive layer is formed of doped polycrystalline silicon.

Claim 25

In a complementary metal-insulator-semiconductor (MIS) integrated circuit device comprising a semiconductor substrate of a first conductivity type, a plurality of well regions of a second conductivity type opposite to that of said substrate and formed in one principal surface of said substrate, said well regions being isolated by p-n junctions, a first metal-insulator-semiconductor field-effect transistor (MISFET) of a first conductivity channel formed in at least a first of said well regions, a second MISFET of a second conductivity channel opposite to that of said first MISFET formed in a portion of the principal surface of said substrate exclusive of said well regions, and a MIS capacitance element formed in the principal surface of said substrate, said MIS capacitance element comprising: an insulator layer formed on the surface of a second of said well regions, a first electrode formed on said insulator layer, said first electrode and said second well region serving respectively as opposite polar electrodes of said MIS capacitance element, and a second electrode for short-circuiting said second well region and said semiconductor substrate.

Claim 26

In a complementary metal-insulator-semiconductor (MIS) integrated circuit device comprising a semiconductor substrate of a first conductivity type, a plurality of well regions of a second conductivity type opposite to that of said substrate and formed in one principal surface of said substrate, said well regions being isolated by p-n junctions, a first metal-insulator-semiconductor field-effect transistor (MISFET) of a first conductivity channel formed in at least a first of said well regions, a second MISFET of a second conductivity channel opposite to that of said first MISFET formed in a portion of the principal surface of said substrate exclusive of said well regions, and a MIS capacitance element formed in the principal surface of said substrate, said MIS capacitance element comprising: an insulator layer formed on the surface of a second of said well regions, a first electrode formed on said insulator layer, said first electrode and said second well region serving respectively as opposite polar electrodes of said MIS capacitance element, and a second electrode for short-circuiting said second well region and said semiconductor substrate.

Claim 27

The capacitance element according to claim 20, wherein said insulator layer has the same thickness as that of each of said first and second MISFETs.

Claim 28

The capacitance element according to claim 21, wherein said first electrode is formed of the same material as that of gate electrodes of said first and second MISFETs.

Claim 29

The capacitance element according to claim 21, wherein said insulator layer is formed of silicon oxide, and said first electrode is formed of doped polycrystalline silicon.

Claim 30

In a metal-insulator-semiconductor (MIS) type capacitance element having a conductive layer, a semiconductor substrate and an insulator layer interposed between said conductive layer and said semiconductor substrate, the improvement comprising said substrate including a first semiconductor region underlying said insulator layer and being defined by a PN junction with a second semiconductor region of said substrate, a dc voltage being applied between said conductive layer and said first semiconductor region with such polarity to prevent generation in the surface of said first semiconductor region of an inversion layer having a conductivity type opposite to that of said first semiconductor region; and means for electrically connecting said first semiconductor region to said second semiconductor region so as to cause said first semiconductor and second semiconductor regions to have the same potential.

Claim 31

In a metal-insulator-semiconductor (MIS) type capacitance element having a conductive layer, a semiconductor substrate and an insulator layer interposed between said conductive layer and said semiconductor substrate, the improvement comprising said substrate including a first semiconductor region underlying said insulator layer and being defined by a PN junction with a second semiconductor region of said substrate, a dc voltage being applied between said conductive layer and said first semiconductor region with such polarity to prevent generation in the surface of said first semiconductor region of an inversion layer having a conductivity type opposite to that of said first semiconductor region; and means for electrically connecting said first semiconductor region to said second semiconductor region so as to cause said first semiconductor and second semiconductor regions to have the same potential.

Claim 32

A capacitance element comprising: a semiconductor substrate of a first conductivity type; a first semiconductor region formed in one principal surface of said semiconductor substrate, and having a second conductivity type opposite to that of said substrate; an insulator layer having a predetermined thickness and disposed on the surface of said first semiconductor region; an electrically conductive layer having a predetermined area and disposed on said insulator layer; said first semiconductor region and said electrically conductive layer serving as opposite polar electrodes of the capacitance element; a dc voltage being applied between said electrodes with such polarity to prevent generation of an inversion layer having a first conductivity type opposite to that of said first semiconductor region in the surface of said first semiconductor region; and means for electrically connecting said first semiconductor region to said semiconductor substrate.

Claim 33

A capacitance element comprising: a semiconductor substrate of a first conductivity type; a first semiconductor region formed in one principal surface of said semiconductor substrate, and having a second conductivity type opposite to that of said substrate; an insulator layer having a predetermined thickness and disposed on the surface of said first semiconductor region; an electrically conductive layer having a predetermined area and disposed on said insulator layer; said first semiconductor region and said electrically conductive layer serving as opposite polar electrodes of the capacitance element; a dc voltage being applied between said electrodes with such polarity to prevent generation of an inversion layer having a first conductivity type opposite to that of said first semiconductor region in the surface of said first semiconductor region; and means for electrically connecting said first semiconductor region to said semiconductor substrate.