Piezoelectric audible indicator circuit

Claim 1

A piezoelectric audible indicator circuit, comprising: (a) a transistor device exhibiting a given collector to emitter breakdown voltage, Vceo, and a given collector to emitter sustaining voltage, Vsus, (b) a two electrode piezoelectric crystal exhibiting a given internal capacitance coupled between the collector and emitter electrodes of said transistor, (c) a collector resistance coupled to said collector electrode, (d) a supply voltage having a magnitude exceeding Vceo and supply means for coupling said supply voltage across the serial connection of said collector resistance and said collector and emitter electrodes, and (e) control means coupled to the base electrode of said transistor for controlling the on-off operation of the circuit by applying during the "off" time a control signal that biases the transistor into its normal conductive state and prevents the circuit from oscillating, and by applying during the "on" time a control signal that biases the transistor so as to oppose normal conduction whereby circuit oscillations result from the internal capacitance of said piezoelectric crystal being sequentially charged through said collector resistance to Vceo and discharged through the transistor conducting in its breakdown mode to Vsus, at which point the transistor once again ceases conduction, the process being cyclically repeated so as to cause said piezoelectric crystal to emit an audible signal.