Method and apparatus for the coding and decoding of digital information

Claim 2

A digital data encoder for encoding a total of M characters, each with a length of m information bits, comprising: (n,k) convolutional encoder means selected such that m≧k; means for feeding each character, followed by k-1 flush bits, to said (n,k) convolutional encoder; M output storage registers, each register of length (mn/k)+(k-1)×((n/k)-1); storing means for storing each convolutionally encoded character M in a predetermined one of said M output storage registers; and output means for outputing the contents of said M output storage registers in a predetermined interleaved sequence.

Claim 3

The digital data encoder of claim 1 wherein: said M output storage registers are arranged in a matrix of M rows and mn/k+(k-1)×((n/k)-1) columns, and wherein said output means outputs the contents of said M output storage registers in a column by column sequence.

Claim 4

The digital data encoder of claim 2 wherein said (n,k) convolutional encoder is comprised of: a shift register of length k into which each m length character followed by k-1 flush bits are sequentially shifted and, parity bit generating means for generating predetermined parity bits dependent upon the status of one or more of the signals in said register, and wherein the storing means includes means for alternately outputing each of the m information bits followed by (n/k)-1 parity bits until all m information bits followed by (n/k)-1 parity bits are stored in one of said M output registers, said output means then outputing (k-1)×(n/k)-1) parity bits to fill said output register.

Claim 5

The digital data encoder of claim 1 wherein said (n,k) convolutional encoder is comprised of: a shift register of length k into which each m length character followed by k-1 flush bits are sequentially shifted and, parity bit generating means for generating predetermined parity bits dependent upon the status of one or more of the signals in said register, and wherein the storing means includes means for alternately outputing each of the m information bits followed by (n/k)-1 parity bits until all m information bits followed by (n/k)-1 parity bits are stored in one of said M output registers, said output means then outputing (k-1)×((n/k)-1) parity bits to fill said output register.

Claim 8

The method of claim 5 wherein said storing step further comprises the step of storing said convolutionally encoded characters in a matrix of M rows and (mn/k)+(k-1)×((n/k)-1) columns and wherein said outputing step comprises outputing the contents of said M output storage registers in a column by column sequence.

Claim 9

The method of claim 5 wherein the step of providing a convolutional encoder further comprises the steps of: (a) providing a shift register of length k, (b) providing parity bit generating means for generating predetermined parity bits dependent upon the status of one or more of the signals in said k length register; and wherein the outputing step comprises the further steps of: (a) storing each of the m information bits followed by (n/k)-1 parity bits until all of said m information bits followed by (n/k)-1 parity bits are stored in one of said M output registers and then (b) outputing (k-1)×((n/k)-1) parity bits to fill said output register.

Claim 10

A decoder for decoding a transmission bit stream comprised of M interleaved characters, each character formed by convolutionally encoding an m bit information character, followed by k-1 flush bits, in an (n,k) convolutional encoder selected such that m≧k, each character having a bit length of (mn/k)+(k-1)×((n/k)-1), the decoder comprising: M input storage registers, each input register having a length (mn/k)+(k-1)×((n/k)-1); means for de-interleaving said M characters from said transmission bit stream and storing each character in a predetermined one of said M input storage registers; an (n,k) convolutional decoder for decoding each of said characters and outputting said m bit information character; M output storage registers, each output register having a length m; and switching means for sequentially processing each character stored in said M input storage registers through said (n,k) convolutional decoder and storing each resulting m bit information character in a predetermined one of said M output registers.

Claim 11

A decoder for decoding a transmission bit stream comprised of M interleaved characters, each character formed by convolutionally encoding an m bit information character, followed by k-1 flush bits, in an (n,k) convolutional encoder selected such that m≧k, each character having a bit length of (mn/k)+(k-1)×((n/k)-1), the decoder comprising: M input storage registers, each input register having a length (mn/k)+(k-1)×((n/k)-1); means for de-interleaving said M characters from said transmission bit stream and storing each character in a predetermined one of said M input storage registers; an (n,k) convolutional decoder for decoding each of said characters and outputting said m bit information character; M output storage registers, each output register having a length m; and switching means for sequentially processing each character stored in said M input storage registers through said (n,k) convolutional decoder and storing each resulting m bit information character in a predetermined one of said M output registers.