Electronic counter

Claim 2

An electronic incrementing/decrementing counter for evaluating impulses representative of both positive and negative increments generated by digital electronic measuring means comprising: register means for counting the impulses generated by the measuring means and generating a first signed integer position reading; memory means for storing a second signed integer position reading previously generated by the register means; comparator means for comparing the first position reading with the second position reading and indicating the result of this comparison at an output; and control means responsive to the output of the comparator means and the sign of the first and second position readings for loading the first position reading into the memory means when the first position reading is a more extreme reading than the second position reading, said control means operative both when the sign of the first and second position readings are disparate and when the sign of the first and second readings are equal.

Claim 3

The counter defined in claim 1 wherein the control means is adapted to selectively function in a first mode in which the control means loads the first position reading into the memory means when the first position reading is greater than the second position reading, and a second mode in which the control means loads the first position reading into the memory means when the first position reading is less than the second position reading.

Claim 4

The counter defined in claim 1 wherein: the memory means comprises a first memory unit adapted to store a second position reading generated by the register means and a second memory unit adapted to store a third position reading generated by the register means; the control means is adapted to operate sequentially in a first and second mode; and further, wherein the control means, when operating in the first mode, causes the comparator means to compare the first and second readings and loads the first reading into the first memory unit if the first reading is greater than the second reading; and when operating in the second mode, causes the comparator means to compare the first and third readings and loads the first reading into the second memory unit if the first reading is less than the third reading such that both the maximum and the minimum readings are automatically determined and stored in the first and second memory units, respectively.

Claim 5

The counter defined in claim 3 further comprising: a third memory unit which is connected with the first and second memory units; and selection means for selectively operating in a first mode in which the selection means loads the contents of the first memory unit into the third memory unit and a second mode in which the selection means loads the contents of the second memory unit into the third memory unit.

Claim 6

The counter defined in claim 1 in which the control means comprises a read only memory.

Claim 7

An electronic incrementing/decrementing counter for evaluating impulses representative of both positive and negative increments generated by digital electronic measuring means comprising: register means for counting the impulses generated by the measurement means to generate a first signed integer position reading; memory means for storing a second reading previously generated by the register means; comparator means for generating an output signal when the magnitude of the first reading is greater than the magnitude of the second reading; control means provided with inputs which report the sign of the first reading, the sign of the second reading, and the output of the comparator means, which control means includes a first test circuit which generates a first test signal when the first reading is positive and the comparator output signal is present; a second test circuit which generates a second test signal when the first and second readings are negative and the comparator output signal is absent; a third test circuit which generates a third test signal when the first reading is positive and the second reading is negative; a fourth test circuit which generates a fourth test signal when the first reading is negative and the comparator output is present; a fifth test circuit which generates a fifth test signal when the first and second readings are positive and the comparator output is absent; a sixth test circuit which generates a sixth test signal when the first reading is negative and the second reading is positive; and mode selection means which causes the control means to selectively function in a first mode in which the first reading is loaded into the memory means when the first, second, or third test signal is generated, and a second mode in which the first reading is loaded into the memory means when the fourth, fifth, or sixth test signal is generated.

Claim 8

An electronic incrementing/decrementing counter for evaluating impulses representative of both positive and negative increments generated by digital electronic measuring means comprising: register means for counting the impulses generated by the measurement means to generate a first signed integer position reading; memory means for storing a second reading previously generated by the register means; comparator means for generating an output signal when the magnitude of the first reading is greater than the magnitude of the second reading; control means provided with inputs which report the sign of the first reading, the sign of the second reading, and the output of the comparator means, which control means includes a first test circuit which generates a first test signal when the first reading is positive and the comparator output signal is present; a second test circuit which generates a second test signal when the first and second readings are negative and the comparator output signal is absent; a third test circuit which generates a third test signal when the first reading is positive and the second reading is negative; a fourth test circuit which generates a fourth test signal when the first reading is negative and the comparator output is present; a fifth test circuit which generates a fifth test signal when the first and second readings are positive and the comparator output is absent; a sixth test circuit which generates a sixth test signal when the first reading is negative and the second reading is positive; and mode selection means which causes the control means to selectively function in a first mode in which the first reading is loaded into the memory means when the first, second, or third test signal is generated, and a second mode in which the first reading is loaded into the memory means when the fourth, fifth, or sixth test signal is generated.