US4156871A
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US
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Analog-to-pulse density converter
Assignee: International Standard Electric Corp
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Filing: 1977-03-03
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Granted: 1979-05-29
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Expires: 1997-03-03
Abstract
Abstract The analog-to-pulse density converter of U.S. Pat. No. 3,955,191 is modified to provide high stability gain with temperature compensation, auto-centering and defined d.c. offset to reduce noise at low signal levels. The modified circuit has reduced power dissipation. The modulator has a stabilized current switching circuit feeding an RC network which is terminated by two D-type flip flops clocked by a high frequency pulse train. Negative feedback from both of the flip flops causes the circuit to generate a pulse density modulated (PDM) output signal related to a given input signal.
Inventors
- 👤 Edward H. Lambourn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:13
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/322; H03M3/324; H03M3/35; H03M3/39; H03M3/412; H03M3/422; H03M3/43; H03M3/436; H03M3/456
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
211 words
An analog-to-digital converter of the pulse density code type comprising: a first bistable trigger circuit having only one conditioning input and a complementing output; first means coupled to said first trigger circuit to apply a clock signal thereto; second means coupled to said conditioning input of said first trigger circuit to apply an analog signal to be digitized thereto; a first feedback circuit coupled from said complementing output to said conditioning input of said first trigger circuit; a second bistable trigger circuit having only one conditioning input coupled to said complementing output of said first trigger circuit and a normal output, said second trigger circuit being coupled to said first means to have said clock signal applied thereto; a second feedback circuit coupled from said normal output of said second trigger circuit to said second means; wherein said first and second feedback circuits are cooperatively constructed so that the amplitude of the signal in said second feedback circuit is substantially less than the amplitude of said analog signal; wherein said first feedback path includes third means for integrating the signal at said complementing output of said first trigger circuit; and wherein said second feedback path includes fourth means for filtering the signal at said normal output of said second trigger circuit.
Claim 2
Dependent Claim
211 words
An analog-to-digital converter of the pulse density code type comprising: a first bistable trigger circuit having only one conditioning input and a complementing output; first means coupled to said first trigger circuit to apply a clock signal thereto; second means coupled to said conditioning input of said first trigger circuit to apply an analog signal to be digitized thereto; a first feedback circuit coupled from said complementing output to said conditioning input of said first trigger circuit; a second bistable trigger circuit having only one conditioning input coupled to said complementing output of said first trigger circuit and a normal output, said second trigger circuit being coupled to said first means to have said clock signal applied thereto; a second feedback circuit coupled from said normal output of said second trigger circuit to said second means; wherein said first and second feedback circuits are cooperatively constructed so that the amplitude of the signal in said second feedback circuit is substantially less than the amplitude of said analog signal; wherein said first feedback path includes third means for integrating the signal at said complementing output of said first trigger circuit; and wherein said second feedback path includes fourth means for filtering the signal at said normal output of said second trigger circuit.
Claim 3
Dependent Claim
44 words
A converter according to claim 1, wherein said second means includes a comparator having said analog signal applied to one terminal, thereof a threshold voltage applied to the other terminal, thereof and an output coupled to said conditioning input of said first trigger circuit.
Claim 4
Dependent Claim
92 words
A converter according to claim 2, further including first and second transistors interconnected to form a current switch, a constant current source coupled to said current switch, and a third feedback path coupled from a complementing output of said second trigger circuit to the base of one of said first and second transistors, said second feedback path being coupled to the base of the other of said first and second transistors, and the collector of said other of said first and second transistors being coupled to said one terminal of said comparator.
Claim 5
Dependent Claim
20 words
A converter according to claim 3, further including fifth means coupled to said constant current source for temperature compensation thereof.
Claim 6
Dependent Claim
49 words
A converter according to claim 4, further including an n-bit pulse counting means coupled to said complementing output of said second trigger circuit, where n is an integer greater than one, and a fourth feedback circuit coupled from said pulse counting means to said one terminal of said comparator.
Claim 7
Dependent Claim
74 words
A converter according to claim 5, wherein said fourth feedback circuit includes sixth means for selecting the most significant bit of n-bit words having a repetition frequency which is sub-division of the frequency of said clock signal, seventh means coupled to said sixth means to integrate signals representing the most significant bits selected, and eighth means coupled to said pulse counting means for resetting thereof at the conclusion of each of said n-bit words.
Claim 8
Dependent Claim
40 words
A converter according to claim 6, wherein said eighth means is capable of being adjusted to reset said n-bit pulse counting means to a condition corresponding to a count m, where m is an integer greater than zero and 0<m<n.
Claim 9
Dependent Claim
73 words
A converter according to claim 7, wherein said sixth means includes a third bistable trigger circuit having a conditioning input coupled to the most significant counting stage of said n-bit pulse counting means, and ninth means coupled to said third bistable trigger circuit to apply a clocking signal equal to said clock signal divided by 2 n thereto, the normal output of said third bistable trigger circuit being coupled to said seventh means.
Claim 10
Dependent Claim
20 words
A converter according to claim 5, further including third means coupled to said constant current source for temperature compensation thereof.
Claim 11
Dependent Claim
50 words
A converter according to claim 9, further including an n-bit pulse counting means coupled to said complementing output of said second trigger circuit, where n is an integer greater than one, and a fourth feedback circuit coupled from said n-bit pulse counting means to said one terminal of said comparator.
Claim 12
Dependent Claim
75 words
A converter according to claim 10, wherein said fourth feedback circuit includes fourth means for selecting the most significant bit of n-bit words having a repetition frequency which is a sub-division of the frequency of said clock signal, fifth means coupled to said fourth means to integrate signals representing the most significant bits selected, and sixth means coupled to said pulse counting means for resetting thereof at the conclusion of each of said n-bit words.
Claim 13
Dependent Claim
60 words
A converter according to claim 8, wherein said n-bit pulse counting means includes at least (n+1) stages to count to (n+1) bits, and further including an OR gate coupled to the n th and the (n+1) th stages of said n-bit pulse counting means, said OR gate having an output coupled to said conditioning input of said third trigger circuit.
Claim 14
Dependent Claim
27 words
A converter according to claim 1, wherein said first feedback path includes third means for integrating the signal at said complementing output of said first trigger circuit.
Claim 15
Dependent Claim
27 words
A converter according to claim 13, wherein said second feedback path includes fourth means for filtering the signal at said normal output of said second trigger circuit.
Claim 16
Dependent Claim
43 words
A converter according to claim 14, wherein said second means includes a comparator having said analog signal applied to one terminal, thereof a threshold voltage applied to the other terminal, and an output coupled to said conditioning input of said first trigger circuit.
Claim 17
Dependent Claim
92 words
A converter according to claim 15, further including first and second transistors interconnected to form a current switch, a constant current source coupled to said current switch, and a third feedback path coupled from a complementing output of said second trigger circuit to the base of one of said first and second transistors, said second feedback path being coupled to the base of the other of said first and second transistors, and the collector of said other of said first and second transistors being coupled to said one terminal of said comparator.
Claim 18
Dependent Claim
20 words
A converter according to claim 16, further including fifth means coupled to said constant current source for temperature compensation thereof.
Claim 19
Dependent Claim
53 words
A converter according to claim 17, further including an n-bit pulse counting means coupled to said complementing output of said second trigger circuit, where n is an integer greater than one, and a fourth feedback circuit coupled from said pulse counting means to said one terminal of said one terminal of said comparator.
Claim 20
Dependent Claim
75 words
A converter according to claim 18, wherein said fourth feedback circuit includes sixth means for selecting the most significant bit of n-bit words having a repetition frequency which is a sub-division of the frequency of said clock signal, seventh means coupled to said sixth means to integrate signals representing the most significant bits selected, and eighth means coupled to said pulse counting means for resetting thereof at the conclusion of each of said n-bit words.
Claim 21
Dependent Claim
40 words
A converter according to claim 19, wherein said eighth means is capable of being adjusted to reset said n-bit pulse counting means to a condition corresponding to a count m, where m is an integer greater than zero and 0<m<n.
Claim 22
Dependent Claim
73 words
A converter according to claim 20, wherein said sixth means includes a third bistable trigger circuit having a conditioning input coupled to the most significant counting stage of said n-bit pulse counting means, and ninth means coupled to said third bistable trigger circuit to apply a clocking signal equal to said clock signal divided by 2 n thereto, the normal output of said third bistable trigger circuit being coupled to said seventh means.
Claim 23
Dependent Claim
59 words
A converter according to claim 21, wherein said n-bit pulse counting means includes at least (n+1) stages to count to (n+1) bits, and further including an OR gate coupled to the n th and the (n+1) stages of said n-bit pulse counting means, said OR gate having an output coupled to said conditioning input of said third trigger circuit.
Claim 24
Dependent Claim
27 words
A converter according to claim 1, wherein said second feedback path includes third means for filtering the signal at said normal output of said second trigger circuit.
Claim 25
Dependent Claim
42 words
A converter according to claim 23, wherein said second means includes a comparator having said analog signal applied to one terminal, a threshold voltage applied to the other terminal, and an output coupled to said conditioning input of said first trigger circuit.
Claim 26
Dependent Claim
93 words
A converter according to claim 24, further including first and second transistors interconnected to form a current switch, a constant current source coupled to said current switch, and a third feedback path coupled from a complementing output of said second trigger circuit to the base of one of said first and second transistors, said second feedback path path being coupled to the base of the other of said first and second transistors, and the collector of said other of said first and second transistors being coupled to said one terminal of said comparator.
Claim 27
Dependent Claim
42 words
A converter according to claim 1, wherein said second means includes a comparator having said analog signal applied to one terminal, a threshold voltage applied to the other terminal, and an output coupled to said conditioning input of said first trigger circuit.
Claim 28
Dependent Claim
89 words
A converter according to claim 26, further including first and second transistors interconnected to form a current switch, a constant current source coupled to said current switch, and a third feedback path coupled from a complementing output of said second trigger circuit to the base of one of said first and second transistors, said second feedback path being coupled to the base of said first and second transistors, and the collector of said other of said first and second transistors being coupled to said one terminal of said comparator.
Claim 29
Dependent Claim
20 words
A converter according to claim 27, further including third means coupled to said constant current source for temperature compensation thereof.
Claim 30
Dependent Claim
92 words
A converter according to claim 1, further including first and second transistors interconnected to form a current switch, a constant current source coupled to said current switch, and a third feedback path coupled from a complementing output of said second trigger circuit to the base of one of said first and second transistors, said second feedback path being coupled to the base of the other of said first and second transistors, and the collector of said other of said first and second transistors being coupled to said one terminal of said comparator.
Claim 31
Dependent Claim
20 words
A converter according to claim 29, further including third means coupled to said constant current source for temperature compensation thereof.
Claim 32
Dependent Claim
49 words
A converter according to claim 30, further including an n-bit pulse counting means coupled to said complementing output of said second trigger circuit, where n is an integer greater than one, and a fourth feedback circuit coupled from said pulse counting means to said one terminal of said comparator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-05-28 | 1982-11-27 | 1983-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-05-28 | 1986-11-27 | 1987-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-05-28 | 1990-11-27 | 1991-05-29 | $7700.00 | Window Closed / Lapsed |