Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
492 words
Remote control system for selection of at least one of a plurality of selectively switchable loads (122) from a central station (110) comprising a bus system (106) having a clock bus (117) and a load switching control bus (129), connected to the central station (110) and to the switchable loads; the central station having a clock source (112); a cyclically operated address counter (115), controlled by the clock source (112), the address counter (115) selecting from said clock pulses a train of a predetermined number of clock pulses to form a selection cycle and a control signal separating sequential selection cycles; means (187) controlled by the address counter (115) connecting clock pulses to the clock bus (117) during a selection portion of the selection cycle and blocking pulses from the clock bus during another portion to thereby form a control signal, defined by a pause in the clock pulses on the clock bus (117) within the selection cycle extending over a predetermined number of clock pulses; a plurality of selectively operable load control switch means (123) to selectively address selected loads and command occurrence of a switching function, the load switch means decoding selected selection pulses corresponding to selected counts of the address count (115) during any selection cycle, for application of said selected pulses to the control bus (129) to address a selected load (122); the loads (122) each including a receiver (111) connected to the clock bus (117) and the load switching control bus (129) and having a receiver counter (130) connected to and counting in synchronism with clock pulses on the clock bus (117) and a decoding circuit (131, 135) connected to the counter and decoding the count of the counter and being responsive to the address of the selected load; and wherein the selection pulses as determined by said selectively operable load control switch means (123) are transmitted over the control bus (129) during the selection portion of the selection cycle in synchronism with the clock pulses on the clock bus (117), said system comprising, in accordance with the invention, in the central station, a pulse generator (181) connected to the bus system (106) to provide function synchronization pulses, the pulse generator being enabled during the control signal separating sequential selection cycles; controlled switch means (197, 198) connected to the clock bus (117) and to the control bus (129) and (a) operable during the selection portion within a selection cycle to connect clock pulses from said clock source (112) to said clock bus (117) and (b) further operable to connect a predetermined number of clock pulses during the control signal portion within the selection cycle formed by the control pause to said control bus (129); and, in each load receiver (112), a function synchronism detection state (156) including a synchronizing counter and connected to the control bus of the bus system to count in synchronism with the pulses derived from the pulse generator (181) in the central station.
Claim 2
Dependent Claim
492 words
Remote control system for selection of at least one of a plurality of selectively switchable loads (122) from a central station (110) comprising a bus system (106) having a clock bus (117) and a load switching control bus (129), connected to the central station (110) and to the switchable loads; the central station having a clock source (112); a cyclically operated address counter (115), controlled by the clock source (112), the address counter (115) selecting from said clock pulses a train of a predetermined number of clock pulses to form a selection cycle and a control signal separating sequential selection cycles; means (187) controlled by the address counter (115) connecting clock pulses to the clock bus (117) during a selection portion of the selection cycle and blocking pulses from the clock bus during another portion to thereby form a control signal, defined by a pause in the clock pulses on the clock bus (117) within the selection cycle extending over a predetermined number of clock pulses; a plurality of selectively operable load control switch means (123) to selectively address selected loads and command occurrence of a switching function, the load switch means decoding selected selection pulses corresponding to selected counts of the address count (115) during any selection cycle, for application of said selected pulses to the control bus (129) to address a selected load (122); the loads (122) each including a receiver (111) connected to the clock bus (117) and the load switching control bus (129) and having a receiver counter (130) connected to and counting in synchronism with clock pulses on the clock bus (117) and a decoding circuit (131, 135) connected to the counter and decoding the count of the counter and being responsive to the address of the selected load; and wherein the selection pulses as determined by said selectively operable load control switch means (123) are transmitted over the control bus (129) during the selection portion of the selection cycle in synchronism with the clock pulses on the clock bus (117), said system comprising, in accordance with the invention, in the central station, a pulse generator (181) connected to the bus system (106) to provide function synchronization pulses, the pulse generator being enabled during the control signal separating sequential selection cycles; controlled switch means (197, 198) connected to the clock bus (117) and to the control bus (129) and (a) operable during the selection portion within a selection cycle to connect clock pulses from said clock source (112) to said clock bus (117) and (b) further operable to connect a predetermined number of clock pulses during the control signal portion within the selection cycle formed by the control pause to said control bus (129); and, in each load receiver (112), a function synchronism detection state (156) including a synchronizing counter and connected to the control bus of the bus system to count in synchronism with the pulses derived from the pulse generator (181) in the central station.
Claim 3
Dependent Claim
47 words
System according to claim 1, wherein the address counter (115) in the central station is disabled during the occurrence of the control pause forming the control signal; and wherein the receiver counter (130), consequently, and during absence of the clock pulses during the control pause, is idle.
Claim 4
Dependent Claim
131 words
System according to claim 1, wherein the pulse generator includes a function synchronization counter (188) counting a predetermined number of clock pulses applied thereto from the clock (112) and providing said predetermined number of clock pulses to the control bus during occurrence of said control signal and when the transfer switch is connected to the control bus; and wherein, in each receiver, a decoding counter (156; 201) is provided, connected to the control bus (129) and sensing occurrence of said predetermined number of function synchronization pulses derived from the function synchronization counter (188) in the central station and providing a synchronization signal to the receiver counter (130) when the receiver synchronization counter (201) has reached a predetermined count number as controlled by the function synchronization pulses on the control bus (129).
Claim 5
Dependent Claim
86 words
System according to claim 3, wherein the receiver synchronization counter (201) has a count input (202) connected to the control bus (129), has a reset input (203) connected to the clock bus (117), and has a count output terminal (204), the count number of which corresponding to the predetermined number of function synchronization pulses being connected to the reset input (113) of the receiver counter (130) to reset the receiver counter (130) each time when the receiver synchronization counter (201) has counted through a count cycle.
Claim 6
Dependent Claim
102 words
System according to claim 3, wherein the function synchronization counter (188) in the central station has a count output of its highest count number (189) connected to reset the address counter (115) and to reset itself at its reset input (192) to synchronize the beginning of counts of the address counter upon the function synchronization counter (188) reaching the highest count; an OR function gate (196) being connected to the count outputs of the function synchronization counter other than the highest count number; and means (197, 185, 128) connecting the output of the OR function gate (196) to the control bus (129).
Claim 7
Dependent Claim
41 words
System according to claim 5, further comprising a bistable stage (190) connected to the highest count output (189) of the function synchronization counter (188), and connection means (195) connecting the reset input (194) of bistable element (190) to the clock (112).
Claim 8
Dependent Claim
160 words
System according to claim 1, wherein the pulse generator (181) includes a function synchronization counter (188); and wherein the function synchronization counter and the address counter (115) comprise shift registers; a differentiating circuit (199) connecting the reset inputs to a source of supply (114); the count inputs (113, 192), respectively, of said address counter and said function synchronization counter being connected to the clock (112) to reset the counters upon first energization of the system by a differentiated switching pulse before the the clock (112) can cause stepping of the counters; and wherein the address counter (115) has its count number output (118) is connected to the count command terminal (183) of the function synchronization counter, and wherein the count command input (193) of the address counter (115) is further connected to the reset input (113) of the address counter (115) to permit the address counter to start counting immediately upon disappearance of a signal on the reset input (113).
Claim 9
Dependent Claim
50 words
System according to claim 1, further comprising a memory circuit (190) connected to the highest count output (189) of the function synchronization counter (188) and providing a reset signal to the reset input (113) of the address counter when the function synchronization counter (188) has counted through a count cycle.
Claim 10
Dependent Claim
45 words
System according to claim 8, wherein one of the integrating circuits (205') and associated with one of the bus lines (117) has a slightly shorter time constant, or energy level response characteristic than the other integrating circuit (205) and connected to the other bus (129).
Claim 11
Dependent Claim
76 words
System according to claim 1, further including integrating circuits (205, 205') connected in advance of the receiver synchronization counter (201) between the respective count input terminal (202) of the receiver synchronization counter (201) and the control bus, and between the reset input (203) of the receiver synchronization counter (201) and the clock bus (117) to filter short-time noise pulses having an energy content substantially different from the pulses commanded by the central station on said buses.
Claim 12
Dependent Claim
37 words
System according to claim 1, wherein the count input terminal (116) of the receiver counter (130) is connected in parallel with the reset input (123) of the receiver synchronizing counter (201); and the reset input has priority.