US4154395A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Redundant signal circuit
Assignee: General Electric Co
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Filing: 1977-11-25
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Granted: 1979-05-15
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Expires: 1997-11-25
Abstract
Abstract The reliability of any system can be enhanced by redundancy. In a turbomachine control system, increased reliability through redundancy is particularly desirable in view of the consequences of an unscheduled shutdown. One area of a turbomachine controls system which is particularly suited to redundant modeling is the speed control circuits. Speed pick-up probes may be subject to severe duty and are critical to the speed control of a turbomachine since they provide the speed feedback signal. The present invention is a solid state circuit which provides an output signal even if either one of two redundant speed feedback probes should fail. This circuit also allows probe replacement while the turbomachine remains in service.
Inventors
- 👤 Thomas A. Fancy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:52
CPC Classifications
F; F02; F02D; F02D41/00; F02D41/0097; F01; F01D; F01D17/00; F01D17/02; F01D17/06; F01D17/20; F01D17/22; F01D17/24; G; G01; G01P; G01P21/00; G01P21/02; G05; G05B; G05B9/00; G05B9/02; G05B9/03
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
151 words
A redundant signal circuit having first and second pulsed input signals and providing an output signal which follows either one of said input signals comprising: first means for dividing one of said input signals into a pair of identical but complementary pulse trains; second means receiving a first portion of the other of said input signals and one of said pulse trains and providing an output signal only upon the failure of the one input signal; an AND gate receiving the output of said second means and a second portion of the other input signal whereby the other input signal will pass through the AND gate only upon the occurrence of a failure in the one input signal; and, an OR gate receiving the other of said pulse trains and the output of said AND gate whereby either one or the other of the input signals will provide the output signal.
Claim 2
Dependent Claim
151 words
A redundant signal circuit having first and second pulsed input signals and providing an output signal which follows either one of said input signals comprising: first means for dividing one of said input signals into a pair of identical but complementary pulse trains; second means receiving a first portion of the other of said input signals and one of said pulse trains and providing an output signal only upon the failure of the one input signal; an AND gate receiving the output of said second means and a second portion of the other input signal whereby the other input signal will pass through the AND gate only upon the occurrence of a failure in the one input signal; and, an OR gate receiving the other of said pulse trains and the output of said AND gate whereby either one or the other of the input signals will provide the output signal.
Claim 3
Dependent Claim
156 words
A redundant signal circuit having at least first and second identical pulsed input signals and providing an output signal which follows either one of said input signals in a predetermined order comprising: first means for dividing one of said input signals into a pair of identical but complementary pulse trains; second means receiving a first portion of the other of said input signals and one of said pulse trains and providing an output signal only upon the failure of the one input signal; an AND gate receiving the output of said second means and a second portion of the other input signal whereby the other input signal will pass through the AND gate only upon the occurrence of a failure in the one input signal; and, an OR gate receiving the other of said pulse trains and the output of said AND gate whereby either one or the other input signals will provide an output signal.
Claim 4
Dependent Claim
156 words
A redundant signal circuit having at least first and second identical pulsed input signals and providing an output signal which follows either one of said input signals in a predetermined order comprising: first means for dividing one of said input signals into a pair of identical but complementary pulse trains; second means receiving a first portion of the other of said input signals and one of said pulse trains and providing an output signal only upon the failure of the one input signal; an AND gate receiving the output of said second means and a second portion of the other input signal whereby the other input signal will pass through the AND gate only upon the occurrence of a failure in the one input signal; and, an OR gate receiving the other of said pulse trains and the output of said AND gate whereby either one or the other input signals will provide an output signal.
Claim 5
Dependent Claim
95 words
A redundant signal circuit having first and second identical input signals and providing an output signal identical to at least one of said input signals comprising: means for dividing said first input signal into two complementary output signals Q and Q; logic means receiving a portion of said second input signal and said Q signal to provide a high output signal upon failure of said first input signal; an AND gate receiving said second input signal and said logic means output signal; and, an OR gate receiving said Q signal and said AND gate output.
Claim 6
Dependent Claim
95 words
A redundant signal circuit having first and second identical input signals and providing an output signal identical to at least one of said input signals comprising: means for dividing said first input signal into two complementary output signals Q and Q; logic means receiving a portion of said second input signal and said Q signal to provide a high output signal upon failure of said first input signal; an AND gate receiving said second input signal and said logic means output signal; and, an OR gate receiving said Q signal and said AND gate output.
Claim 7
Dependent Claim
15 words
The circuit recited in claim 3 wherein said signal dividing means is a monostable multivibrator.
Claim 8
Dependent Claim
21 words
The circuit recited in claim 3 wherein said logic means comprises a dual flip-flop circuit with clear by said Q signal.
Claim 9
Dependent Claim
128 words
A redundant signal circuit for transmitting at least two independent pulsed signals proportional to measured speed into a speed feedback circuit comprising: first and second input signal channels including identical signal conditioning means; a monostable multivibrator circuit in said first signal channel providing Q and Q outputs proportional to said first channel input signal; a dual J-K flip-flop circuit including one input from said second signal channel and a second input comprising the Q output, said Q input providing a clear signal; an AND gate having a first input connected to the J-K flip-flop circuit output and a second input connected to said second channel; and, an OR gate having a first input connected to the Q output and a second input connected to said AND gate output.
Claim 10
Dependent Claim
128 words
A redundant signal circuit for transmitting at least two independent pulsed signals proportional to measured speed into a speed feedback circuit comprising: first and second input signal channels including identical signal conditioning means; a monostable multivibrator circuit in said first signal channel providing Q and Q outputs proportional to said first channel input signal; a dual J-K flip-flop circuit including one input from said second signal channel and a second input comprising the Q output, said Q input providing a clear signal; an AND gate having a first input connected to the J-K flip-flop circuit output and a second input connected to said second channel; and, an OR gate having a first input connected to the Q output and a second input connected to said AND gate output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-05-14 | 1982-11-13 | 1983-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-05-14 | 1986-11-13 | 1987-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-05-14 | 1990-11-13 | 1991-05-15 | $7700.00 | Window Closed / Lapsed |