US4151367A
Expired / Lapsed
US
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Data sync acquisition in an asynchronous binary address decoder
Assignee: Motorola Solutions Inc
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Filing: 1977-04-29
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Granted: 1979-04-24
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Expires: 1997-04-29
Abstract
Abstract Synchronization for data sampling pulses in a two-way alphanumeric data terminal is provided by utilization of signals present in the page address decoder circuitry. Microprocessor power-up timing is also obtained from the same signals.
Inventors
- 👤 John D. Nicolini
- 👤 David F. Willard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 00:16
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/041; H04L7/042; H04W; H04W88/00; H04W88/02; H04W88/022; H04W88/025; H04W88/026
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
247 words
In an apparatus for detecting, sampling and decoding binary-coded address words and message bits contained within a received train of pulses, circuitry for providing a synchronizing pulse for the sampling of said message bits and comprising in combination: timing means for providing a first timing pulse during each address sampling period; first bistable circuit means for providing a signal enabling the detection of selected ones of the address words; detect circuit means for providing a page detect pulse in response to the detection of the binary address; first gating means coupled to the bistable means for being enabled by a level transition of the word select enabling signal, and to the timing means for providing an output signal in response to the next subsequent timing pulse from the timing means; second bistable means coupled to the detect circuit means for being set by the page detect pulse and coupled to the first gating means for being reset by the output signal of the gating means; second gating means coupled to the first bistable circuit means for initiating a sync pulse in response to a level transition of the work select enabling signal and to the second bistable means for ending said sync pulse in response to a level transition in the output signal of said second bistable means; and sampling means for receiving the message bits and coupled to the output of the second gating means for providing message bit sampling pulses synchronized by said sync pulse.
Claim 2
Dependent Claim
247 words
In an apparatus for detecting, sampling and decoding binary-coded address words and message bits contained within a received train of pulses, circuitry for providing a synchronizing pulse for the sampling of said message bits and comprising in combination: timing means for providing a first timing pulse during each address sampling period; first bistable circuit means for providing a signal enabling the detection of selected ones of the address words; detect circuit means for providing a page detect pulse in response to the detection of the binary address; first gating means coupled to the bistable means for being enabled by a level transition of the word select enabling signal, and to the timing means for providing an output signal in response to the next subsequent timing pulse from the timing means; second bistable means coupled to the detect circuit means for being set by the page detect pulse and coupled to the first gating means for being reset by the output signal of the gating means; second gating means coupled to the first bistable circuit means for initiating a sync pulse in response to a level transition of the work select enabling signal and to the second bistable means for ending said sync pulse in response to a level transition in the output signal of said second bistable means; and sampling means for receiving the message bits and coupled to the output of the second gating means for providing message bit sampling pulses synchronized by said sync pulse.
Claim 3
Dependent Claim
61 words
The apparatus of claim 1 wherein the synchronizing pulse circuitry further includes an initializing circuit and third and fourth gating means, the third gating means being coupled between the first bistable means and the first gating means, the fourth gating means being coupled between the timing means and the first gating means being coupled for being enabled by the initializing circuit.
Claim 4
Dependent Claim
41 words
The apparatus of claim 1 and further including delay means coupled to receive the synchronizing pulse and adapted to provide an interrupt signal to the decoder portion of the apparatus, said signal beginning a predetermined period subsequent to the synchronizing pulse.
Claim 5
Dependent Claim
38 words
The apparatus of claim 3 wherein the delay means includes a counter means coupled to the timing means for counting the output pulses of said timing means, and providing an output at the end of said predetermined period.
Claim 6
Dependent Claim
43 words
The apparatus of claim 4 wherein the delay means further includes a latching means coupled for being reset by said sync pulse and for being enabled by said delayed sync pulse and for being actuated by the next subsequent timing pulse after enablement.
Claim 7
Dependent Claim
61 words
The apparatus according to claim 1 wherein the timing means provides an additional pulse preceding each of said first timing pulses and wherein the delay means further includes a latching means coupled for being reset by said sync pulse and for being enabled by said delayed sync pulse and for being actuated by the next subsequent additional timing pulse after enablement.
Claim 8
Dependent Claim
245 words
In an apparatus for detecting, sampling and decoding binary-coded address words and message bits contained within a received train of pulses, circuitry for providing a synchronizing pulse for the sampling of said message bits and comprising in combination: a first signal source for providing a first timing pulse during each address sampling period; a second signal source for providing a signal enabling the detection of selected ones of the address words; a third signal source for providing a page detect pulse in response to the detection of the binary addres; first gating means coupled to the first and second signal sources for being enabled by a level transition of the word select enabling signal and for providing an output signal in response to the next subsequent pulse from the first signal source; bistable means coupled to the third signal source for being set by the page detect pulse and coupled to the first gating means for being reset by the output signal of the gating means; second gating means coupled to the second signal source for initiating a sync pulse in response to a level transition of the word select enabling signal and to the bistable means for ending said sync pulse in response to a level transition in the output signal of said bistable means; and sampling means for receiving the message bits and coupled to the output of the second gating means for providing message bit sampling pulses synchronized by said sync pulse.
Claim 9
Dependent Claim
245 words
In an apparatus for detecting, sampling and decoding binary-coded address words and message bits contained within a received train of pulses, circuitry for providing a synchronizing pulse for the sampling of said message bits and comprising in combination: a first signal source for providing a first timing pulse during each address sampling period; a second signal source for providing a signal enabling the detection of selected ones of the address words; a third signal source for providing a page detect pulse in response to the detection of the binary addres; first gating means coupled to the first and second signal sources for being enabled by a level transition of the word select enabling signal and for providing an output signal in response to the next subsequent pulse from the first signal source; bistable means coupled to the third signal source for being set by the page detect pulse and coupled to the first gating means for being reset by the output signal of the gating means; second gating means coupled to the second signal source for initiating a sync pulse in response to a level transition of the word select enabling signal and to the bistable means for ending said sync pulse in response to a level transition in the output signal of said bistable means; and sampling means for receiving the message bits and coupled to the output of the second gating means for providing message bit sampling pulses synchronized by said sync pulse.
References Cited (Backward Citations)
US4010421A
Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-23 | 1982-10-23 | 1983-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-23 | 1986-10-23 | 1987-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-23 | 1990-10-23 | 1991-04-24 | $7700.00 | Window Closed / Lapsed |