US4150426A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistorized power supply drive circuit arrangement
Assignee: US Philips Corp
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Filing: 1977-11-23
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Granted: 1979-04-17
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Expires: 1997-11-23
Abstract
Abstract In a switched mode power supply of the push-pull type the drive to each output transistor is terminated just after its collector current reaches the value which the collector current of the other transistor had when the drive thereto was removed in the immediately preceding conduction period, in order to substantially equalize the drive to the output transformer contributed by each output transistor. This is done by means of sampling and storage circuits which store signals representative of the values of the collector currents in the two output transistors which occur when their drive is removed in combination with a comparison circuit which compares each stored value with the collector current of that transistor which conducts during the next conduction period.
Inventors
- 👤 Leonard E. Jansson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:22
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/22; H02M3/24; H02M3/28; H02M3/325; H02M3/335; H02M3/337; H02M3/3376; H02M3/3378
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
279 words
A current-balancing circuit for a direct-voltage converter of the push-pull type comprising, a transformer having a primary winding adapted to be alternately connected to a direct voltage source by means of at least two transistors so that an alternating voltage is obtained in a secondary winding of the transformer, a drive circuit producing pulses for alternately driving the transistors into conduction in a pulsating fashion, current measuring means connected in series with the main current paths of the transistors, a comparison circuit which includes output means which supply correction signals to the drive circuit in the case of inequality of the currents in the main current paths in a manner so as to eliminate said inequality, a first and a second sampling and storage circuit each having a measuring input connected to the current measuring means, a control input connected to the drive circuit, and a measuring output connected to an input of the comparison circuit, and means connecting another input of the comparison circuit to the current measuring means, whereby during each pulse from the drive circuit which causes one of the transistors to conduct one sampling and storage circuit is operative to store the value of the current through the conducting transistor, the final value of the current in the other transistor upon termination of the preceding pulse from the drive circuit being transferred from the measuring output of the other sampling and storage circuit to the comparison circuit which compares said final value with the said value of the current through the conducting transistor and produces an output signal to terminate the existing pulse when the said value of the current exceeds the said final value.
Claim 2
Dependent Claim
279 words
A current-balancing circuit for a direct-voltage converter of the push-pull type comprising, a transformer having a primary winding adapted to be alternately connected to a direct voltage source by means of at least two transistors so that an alternating voltage is obtained in a secondary winding of the transformer, a drive circuit producing pulses for alternately driving the transistors into conduction in a pulsating fashion, current measuring means connected in series with the main current paths of the transistors, a comparison circuit which includes output means which supply correction signals to the drive circuit in the case of inequality of the currents in the main current paths in a manner so as to eliminate said inequality, a first and a second sampling and storage circuit each having a measuring input connected to the current measuring means, a control input connected to the drive circuit, and a measuring output connected to an input of the comparison circuit, and means connecting another input of the comparison circuit to the current measuring means, whereby during each pulse from the drive circuit which causes one of the transistors to conduct one sampling and storage circuit is operative to store the value of the current through the conducting transistor, the final value of the current in the other transistor upon termination of the preceding pulse from the drive circuit being transferred from the measuring output of the other sampling and storage circuit to the comparison circuit which compares said final value with the said value of the current through the conducting transistor and produces an output signal to terminate the existing pulse when the said value of the current exceeds the said final value.
Claim 3
Dependent Claim
63 words
A current balancing circuit as claimed in claim 1, wherein the comparison circuit includes a first and a second comparator each having a blocking input connected to the output of a time delay circuit, and means connecting a trigger input of the time delay circuit to the drive circuit for blocking a comparator during the beginning of each drive pulse for the transistors.
Claim 4
Dependent Claim
32 words
A current balancing circuit as claimed in claim 2, characterized in that the control input of the sampling and storage circuit is connected to said drive circuit via the time delay circuit.
Claim 5
Dependent Claim
126 words
A current balancing circuit as claimed in claim 2 wherein the drive circuit includes a clock pulse generator which supplies basic pulses from which the drive pulses for the transistors are derived, characterized in that the control input of a sampling and storage circuit is connected to the drive circuit via an OR-gate having an output connected to said control input and a first input connected to the output of the time delay circuit and a second input connected to a pulse generator circuit which has a blocking input connected to said trigger input and a start input connected to the clock pulse generator, whereby a sampling pulse is only supplied to said control input in the absence of a control pulse during a basic pulse.
Claim 6
Dependent Claim
234 words
A current balancing circuit as claimed in claim 1 wherein the comparison circuit includes one common comparator having a pair of blocking inputs connected to the output of a time delay circuit, means connecting a trigger input of the time delay circuit to the drive circuit, and the first and second sampling and storage circuits each comprise a series connection of a capacitor and a switch having a control electrode, which series connection is connected across the sampling and storage circuit measuring input, the control electrode of the switch being the respective control input and the junction point of the switch and capacitor being the respective measuring output, the measuring inputs being connected in parallel with each other and to a common current measuring means, the one common comparator further comprising a differential amplifier and two further switches each having a control electrode, the output of the amplifier being connected to a control input of the drive circuit, one input of the amplifier being connected to one terminal of each of the two further switches, the other terminal of each of said two further switches being connected to a said respective measuring output, and the control electrode of each further switch being connected to a respective blocking input, and a second input of the amplifier is connected to a common line which connects the measuring inputs and to which the first-mentioned switches are connected.
Claim 7
Dependent Claim
34 words
A current balancing circuit as claimed in claim 5 further comprising means connecting each measuring output via a clamping diode to a reference potential which corresponds to a maximum permissible current in the transistors.
References Cited (Backward Citations)
US3657631A
Cited
US3737756A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-16 | 1982-10-16 | 1983-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-16 | 1986-10-16 | 1987-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-16 | 1990-10-16 | 1991-04-17 | $7700.00 | Window Closed / Lapsed |