Patent US2160981A successfully refreshed from Google Patents.
US4149151A
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US
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Display data synthesizer circuit
Assignee: Hitachi Ltd
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Filing: 1977-05-20
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Granted: 1979-04-10
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Expires: 1997-05-20
Abstract
Abstract A display data synthesizer circuit is used for a display panel having a multiplicity of display elements selectively excited for display of the desired pattern of characters or symbols. The display elements are divided into a plurality of sections which are sequentially driven and in driving each section, selected display elements of that section are excited simultaneously for a predetermined period of time, by sequentially synthesizing and holding the display data for the respective sections in the order of the driving operations thereof. The circuit includes a series output shift register and a parallel output shift register. The series output shift register stores a plurality of bits included in a display data for one section, applied thereto bit-serially at a first repetitive speed, and outputs the stored data at a second repetitive speed higher than the first repetitive speed. The parallel output shift register receives bit-serially the display data derived from the series output shift register, and holding it for a predetermined period of time, applies it bit parallelly to the drive circuit of the display panel for that same period. The series output shift register receives and stores the display data for the next section during the time when the parallel output shift register applies the display data held thereby to the drive circuit. The second repetitive speed is so selected as to make the data transfer time from the series output shift register to the parallel output shift register sufficiently short so that the display disturbances of the display panel are not substantially recognized visually.
Inventors
- 👤 Yoshiharu Nagae
- 👤 Hideaki Kawakami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:11
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3685; G09G5/00; G09G5/22; G09G5/222
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
214 words
A display data synthesizer circuit used with a display panel including a multiplicity of display elements for display of a desired pattern by selectively exciting said display elements, said display elements being divided into a plurality of sections to be sequentially scanned and driven, said display data synthesizer circuit serving to synthesize and hold display data for each of said sections for a predetermined period of time in order to selectively excite said display elements in said each section for said predetermined period of time; said display data synthesizer circuit comprising a series output shift register for receiving bit-serially a plurality of bits of display data for one section of display elements at a first repetitive speed and producing them bit-serially at a second repetitive speed higher than said first repetitive speed; and a parallel output shift register for receiving the display data from said series output shift register and for holding it for a predetermined period of time, said parallel output shift register producing said display data bit-parallely for driving said display elements in said each section; said first repetitive speed being so selected that said display data receiving operation of said series output shift register is performed within a time interval during which said parallel output shift register produces said display data.
Claim 2
Dependent Claim
214 words
A display data synthesizer circuit used with a display panel including a multiplicity of display elements for display of a desired pattern by selectively exciting said display elements, said display elements being divided into a plurality of sections to be sequentially scanned and driven, said display data synthesizer circuit serving to synthesize and hold display data for each of said sections for a predetermined period of time in order to selectively excite said display elements in said each section for said predetermined period of time; said display data synthesizer circuit comprising a series output shift register for receiving bit-serially a plurality of bits of display data for one section of display elements at a first repetitive speed and producing them bit-serially at a second repetitive speed higher than said first repetitive speed; and a parallel output shift register for receiving the display data from said series output shift register and for holding it for a predetermined period of time, said parallel output shift register producing said display data bit-parallely for driving said display elements in said each section; said first repetitive speed being so selected that said display data receiving operation of said series output shift register is performed within a time interval during which said parallel output shift register produces said display data.
Claim 3
Dependent Claim
61 words
A display data synthesizer circuit according to claim 1, in which said series output shift register includes a plurality of register sections for storing respective data groups in which said display data is divided, the data of each data group being transferred bit-serially to said parallel output shift register and the data transfers from respective data groups being carried out parallely.
Claim 4
Dependent Claim
59 words
A display data synthesizer circuit according to claim 1, in which said second repetitive speed is so selected that data transfer from said series output shift register to said parallel output shift register is completed within a time not longer than 5% of said predetermined period of time during which each display elements section is selected to be scanned.
Claim 5
Dependent Claim
59 words
A display data synthesizer circuit according to claim 2, in which said second repetitive speed is so selected that data transfer from said series output shift register to said parallel output shift register is completed within a time not longer than 5% of said predetermined period of time during which each display elements section is selected to be scanned.
Claim 6
Dependent Claim
210 words
A display panel of liquid crystal matrix type including a multiplicity of liquid crystal display elements arranged in lines and rows; said display panel comprising a display data synthesizer circuit for synthesizing line display data for the display elements included in each of said lines and holding said line display data for a predetermined period of time in order to sequentially scan and drive said lines and to selectively excite the display elements in each line during said predetermined period of time, said display data synthesizer circuit including a series output shift register for writing bit-serially the line display data for one line at a first repetitive speed and for producing said line display data bit-serially at a second repetitive speed higher than said first repetitive speed, and a parallel output shift register for receiving the line display data from said series output shift register and holding it for a predetermined period of time, said parallel output shift register producing the line display data bit-serially for driving the display elements in said line, said first repetitive speed being so selected that said display data writing operation of said series output shift register is performed in a time interval during which said parallel output shift register produces said line display data.
Claim 7
Dependent Claim
210 words
A display panel of liquid crystal matrix type including a multiplicity of liquid crystal display elements arranged in lines and rows; said display panel comprising a display data synthesizer circuit for synthesizing line display data for the display elements included in each of said lines and holding said line display data for a predetermined period of time in order to sequentially scan and drive said lines and to selectively excite the display elements in each line during said predetermined period of time, said display data synthesizer circuit including a series output shift register for writing bit-serially the line display data for one line at a first repetitive speed and for producing said line display data bit-serially at a second repetitive speed higher than said first repetitive speed, and a parallel output shift register for receiving the line display data from said series output shift register and holding it for a predetermined period of time, said parallel output shift register producing the line display data bit-serially for driving the display elements in said line, said first repetitive speed being so selected that said display data writing operation of said series output shift register is performed in a time interval during which said parallel output shift register produces said line display data.
Claim 8
Dependent Claim
62 words
A display data synthesizer circuit according to claim 5, in which said series output shift register includes a plurality of register sections for storing respective data groups in which said line display data is divided, data of each of said groups being transferred bit-serially to said parallel output shift register, and the data transfers from respective data groups being carried out parallely.
Claim 9
Dependent Claim
58 words
A display data synthesizer circuit according to claim 5, in which said second repetitive speed is so selected that data transfer from said series output shift register to said parallel output shift register is completed within a time not longer than 5% of said predetermined period of time during which said each line is selected to be scanned.
Claim 10
Dependent Claim
58 words
A display data synthesizer circuit according to claim 6, in which said second repetitive speed is so selected that data transfer from said series output shift register to said parallel output shift register is completed within a time not longer than 5% of said predetermined period of time during which said each line is selected to be scanned.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-09 | 1982-10-09 | 1983-04-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-09 | 1986-10-09 | 1987-04-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-09 | 1990-10-09 | 1991-04-10 | $7700.00 | Window Closed / Lapsed |