Circuit arrangement for linearizing the output signal of a test sensor

Claim 1

A circuit for linearizing the output signal of a measuring sensor, comprising: clock means for generating electrical clock pulses at a fixed pulse frequency; first frequency divider means for receiving said clock pulses and generating corresponding first divider output pulses at a fixed frequency defined by a characteristic fixed dividing factor of said first divider; first pulse counter means for counting the pulses generated by said first frequency divider and generating a first counter output signal corresponding to the instantaneous number of pulses counted; second frequency divider means for receiving said clock pulses and generating second divider output pulses at a variable frequency defined by a variable dividing factor of said second divider; second pulse counter means for counting the pulses generated by said second frequency divider and generating a second counter output signal corresponding to the instantaneous number of pulses counted; control means for periodically setting a particular dividing factor value into said second frequency divider to vary the dividing factor of said second frequency divider so that the count of said second pulse counter varies as a function of time during each period of measurement according to the measuring sensor characteristic to be linearized; comparator means for receiving the instantaneous output signal of the sensor and an analog signal corresponding to said second counter output signal, and generating a strobe signal when the analog signal and the instantaneous sensor output signal are equal; and memory means responsive to said strobe signal to generate an output signal corresponding to the instantaneous count of said first pulse counter when said strobe signal is generated.