Memory device having a reduced number of pins

Claim 2

A memory device requiring a power signal and a reference signal, comprising: a memory element; at least two external terminals, one of said external terminals for receiving a first signal and the other of said external terminals for receiving a second signal; threshold detection means operatively connected to said external terminals for sensing when the difference in magnitude of said first and second signals reaches a predetermined level and in response thereto providing an enabling signal at its output; and means for receiving said enabling signal and in response thereto causing said power and reference signals to be provided by said first and second signals.

Claim 3

The memory device of claim 1, wherein said first signal includes substantially periodic clock pulses and wherein said memory device further comprises an internal power supply having a power terminal for receiving said power signal and a reference terminal for receiving said reference signal and capacitor means connected across the leads to said power and reference terminals of said internal power supply.

Claim 4

In a memory device having at least two external pins and requiring a power signal and a ground level signal: signal processing means for receiving a first signal applied to one of said external pins and a second signal applied to the other of said external pins, said first and second signals providing functions other than power and ground signal functions, and for processing said first and second signals to provide said power and ground level signals, said processing means including a threshold detector operatively connected to said two external pins for generating an enabling signal when the difference in the magnitude of said first and second signals reaches a predetermined level.

Claim 5

In a memory device having at least two external pins and requiring a power signal and a ground level signal: signal processing means for receiving a first signal applied to one of said external pins and a second signal applied to the other of said external pins, said first and second signals providing functions other than power and ground signal functions, and for processing said first and second signals to provide said power and ground level signals, said processing means including a threshold detector operatively connected to said two external pins for generating an enabling signal when the difference in the magnitude of said first and second signals reaches a predetermined level.

Claim 6

The memory device of claim 3, wherein said first signal includes substantially periodic clock pulses and wherein said processing means comprises rectification means and further includes a capacitor and switching means for receiving the enabling signal from said threshold detector and in response thereto connecting the one of said external pins to said capacitor so that a relatively constant voltage is maintained across said capacitor to provide said power and ground level signals.

Claim 7

In a memory device having an internal power supply for receiving a power signal and a ground level signal; a first pin for receiving a first, substantially periodic signal; a second pin for receiving a second signal; and rectification circuit means, including a threshold detector operatively connected to said first and second pins for receiving said first and second signals and for sensing the difference in voltage of said first and second signals, and when a maximum voltage difference level is sensed, for causing said first and second signals to provide said power signal and said ground level signal to said internal power supply.

Claim 8

In a memory device having an internal power supply for receiving a power signal and a ground level signal; a first pin for receiving a first, substantially periodic signal; a second pin for receiving a second signal; and rectification circuit means, including a threshold detector operatively connected to said first and second pins for receiving said first and second signals and for sensing the difference in voltage of said first and second signals, and when a maximum voltage difference level is sensed, for causing said first and second signals to provide said power signal and said ground level signal to said internal power supply.

Claim 9

The memory device of claim 5, wherein said threshold detector generates an enabling signal when the maximum difference level is sensed, and wherein said rectification circuit means further includes switching means for receiving said enabling signal and in response thereto connecting said first pin to a first, power input terminal of the internal power supply, and said second pin to a second, ground input terminal of said internal power supply.

Claim 10

The memory device of claim 6, wherein said switching means includes a first and a second transistor for receiving said enabling signal, said first transistor interposed between said first external pin and said first input terminal of said internal power supply and said second transistor interposed between said second external pin and said second input terminal of said internal power supply.

Claim 11

The memory device of claim 7, wherein said switching means further includes a third transistor for receiving said enabling signal by way of an inverter and being interposed between said first external pin and said second input terminal of said internal power supply so that said first pin is connected to said second terminal when the maximum difference level is not sensed by said threshold detector.

Claim 12

The memory device of claim 5, wherein said rectification circuit means further includes capacitor means connected across said first and second input terminals of said internal power supply so that a substantially constant voltage difference is maintained across said first and second input terminals of said internal power supply.

Claim 13

In a memory device in the form of an integrated circuit structure: a first pin for receiving a first synchronizing signal; means for detecting a change in said first synchronizing signal for enabling said memory device; a second pin for receiving a second signal, including memory address, data input, and internally-generated data output component signals; means for mode selecting said memory device in response to a mode select signal at one of said first and second external pins; an internal power supply for receiving a power signal and a ground level signal; and rectification means for receiving the first signal and the second signal on said first and second external pins and in response thereto providing said power signal and said ground level signal to said internal power supply, said rectification means including switching means and threshold detector means, said threshold detector means for providing an enabling signal when a predetermined difference in voltage between said first and second signals is sensed, said switching means for receiving said enabling signal and in response thereto for operatively connecting said first and second external pins to said power supply.

Claim 14

In a memory device in the form of an integrated circuit structure: a first pin for receiving a first synchronizing signal; means for detecting a change in said first synchronizing signal for enabling said memory device; a second pin for receiving a second signal, including memory address, data input, and internally-generated data output component signals; means for mode selecting said memory device in response to a mode select signal at one of said first and second external pins; an internal power supply for receiving a power signal and a ground level signal; and rectification means for receiving the first signal and the second signal on said first and second external pins and in response thereto providing said power signal and said ground level signal to said internal power supply, said rectification means including switching means and threshold detector means, said threshold detector means for providing an enabling signal when a predetermined difference in voltage between said first and second signals is sensed, said switching means for receiving said enabling signal and in response thereto for operatively connecting said first and second external pins to said power supply.

Claim 17

The method of claim 11, wherein said step of providing a first signal includes alternating said first signal between a power level voltage and a ground level voltage, and wherein said step of providing a second signal includes providing said second signal at its ground level voltage when said first signal is at its power voltage level.