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US4144753A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit arrangement for determining physical parameters of flowing media by the ultrasonic method

Assignee: Danfoss AS
•
Filing: 1977-08-12
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Granted: 1979-03-20
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Expires: 1997-08-12
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Abstract

Abstract The invention relates to a circuit for determining the arrival time of an ultrasonic signal. The circuit includes a differentiator for transforming an ultrasonic signal to a substantially linearly increasing signal, and a threshold value detector for transforming the linearly increasing signal to an arrival delay signal. A phase detector in the form of a D-type flip-flop determines the phase position of the arrival delay signal relative to a reference signal. The phase detector generates early signals on early arrival of the delay signal and late signals on late arrival of the delay signal. A regulator integrator is provided between the phase detector and the differentiator for producing an output voltage for altering the delay period of the arrival delay signal responsive to the phase position of the delay signal. Resetting apparatus is provided between the regulator integrator and the phase detector for resetting the integrator when the output voltage reaches a predetermined maximum or minimum value to cause the output voltage to return to zero. The resetting apparatus includes hysteresis for maintaining resetting signals until the output voltage is substantially zero.

Inventors

  • 👤 Poul M. Larsen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 17:54
CPC Classifications
G; G01; G01P; G01P5/00; G01P5/24; G01P5/245; G01F; G01F1/00; G01F1/66; G01F1/667; G01N; G01N2291/00; G01N2291/02; G01N2291/028; G01N2291/02836

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 158 words
A circuit for determining the arrival time of an ultrasonic signal, comprising, means for transforming said ultrasonic signal to a substantially linearly increasing signal, threshold value detector means for transforming said linearly increasing signal to an arrival delay signal, phase detector means for determining the phase position of said arrival delay signal relative to a reference signal, said phase detector means generating early signals on early arrival of said delay signal and generating late signals on late arrival of said delay signal, regulator integrator means between said phase detector means and said threshold value detector means producing an output voltage for altering the delay period of said arrival delay signal responsive to the phase position of said delay signal, resetting means between said regulator integrator means and said phase detector means for resetting said integrator means to zero when said output voltage reaches a predetermined maximum or minimum value to cause said output voltage to return to zero.
Claim 2
Dependent Claim 158 words
A circuit for determining the arrival time of an ultrasonic signal, comprising, means for transforming said ultrasonic signal to a substantially linearly increasing signal, threshold value detector means for transforming said linearly increasing signal to an arrival delay signal, phase detector means for determining the phase position of said arrival delay signal relative to a reference signal, said phase detector means generating early signals on early arrival of said delay signal and generating late signals on late arrival of said delay signal, regulator integrator means between said phase detector means and said threshold value detector means producing an output voltage for altering the delay period of said arrival delay signal responsive to the phase position of said delay signal, resetting means between said regulator integrator means and said phase detector means for resetting said integrator means to zero when said output voltage reaches a predetermined maximum or minimum value to cause said output voltage to return to zero.
Claim 3
Dependent Claim 69 words
A circuit according to claim 1 wherein said resetting means has two branches for generating first and second resetting signals respectively when said output voltage exceeds a positive limiting value or falls below a negative limiting value, said phase detector means applying input pulses to either the inverting or noninverting inputs of said integrator means on the occurrence of one or the other of said resetting branches being activated.
Claim 4
Dependent Claim 25 words
A circuit according to claim 2 wherein each of said branches has comparator means with hysteresis in the form of a differential amplifier with feedback.
Claim 5
Dependent Claim 24 words
A circuit according to claim 1 wherein said resetting means includes hysteresis means for maintaining resetting signals until said output voltage is substantially zero.
Claim 6
Dependent Claim 24 words
A circuit according to claim 2 wherein said phase detector means includes a flip-flop with setting and clearing inputs connected respectively to said branches.
Claim 7
Dependent Claim 36 words
A circuit according to claim 5 wherein said flip-flop is a D-type with data a clock inputs, said reference signal being applied to said data input and said delay signal being applied to said clock input.

References Cited (Backward Citations)

US4022058A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1982-03-19 1982-09-18 1983-03-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1986-03-19 1986-09-18 1987-03-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1990-03-19 1990-09-18 1991-03-20 $7700.00 Window Closed / Lapsed

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