US4144525A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Cascadable analog to digital converter
Assignee: AT&T Inc
•
Filing: 1977-10-21
•
Granted: 1979-03-13
•
Expires: 1997-10-21
Abstract
Abstract A circuit for converting an input analog signal into a digital representation and a remainder signal is disclosed. The digital representation is generated by a coder that counts an integral number of clock cycles during an interval in which the magnitude of the input analog signal is compared with the magnitude of a ramp signal. The remainder signal is generated by duration-to-amplitude conversion of a pulse whose duration is the fractional remainder of the final uncounted clock cycle.
Inventors
- 👤 John F. O'Neill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:08
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/14; H03M1/16; H03M1/34; H03M1/38; H03M1/44; H03M1/50; H03M1/56
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
99 words
A circuit for converting an analog signal level into a digital approximation and a remainder signal, said remainder signal being a measure of the error between the analog signal level and the digital approximation, including means for converting the analog signal level into a duration modulated signal and means for counting discrete events of a timing signal during the duration of said duration modulated signal, characterized by: means responsive to an interval between the termination of the duration modulated signal and a timing signal discrete event which is adjacent in time to said termination, for generating the remainder signal.
Claim 2
Dependent Claim
99 words
A circuit for converting an analog signal level into a digital approximation and a remainder signal, said remainder signal being a measure of the error between the analog signal level and the digital approximation, including means for converting the analog signal level into a duration modulated signal and means for counting discrete events of a timing signal during the duration of said duration modulated signal, characterized by: means responsive to an interval between the termination of the duration modulated signal and a timing signal discrete event which is adjacent in time to said termination, for generating the remainder signal.
Claim 3
Dependent Claim
29 words
A ciruit according to claim 1 wherein the converting means includes means for comparing the magnitude of the analog signal level with the magnitude of a time varying signal.
Claim 4
Dependent Claim
13 words
A circuit according to claim 1 wherein the generating means includes duration-to-amplitude conversion.
Claim 5
Dependent Claim
16 words
A circuit according to claim 3 wherein amplification is controllably provided in the duration-to-amplitude conversion process.
Claim 6
Dependent Claim
39 words
A circuit according to claim 1 wherein the generating means is responsive to the interval extending between the termination of the duration modulated signal and the next discrete event of the timing signal for generating a complementary remainder signal.
Claim 7
Dependent Claim
112 words
In a multistage analog to digital converter wherein each stage generates a portion of a digital representation of an analog signal level, the portion being formed by means for counting discrete events of a timing signal occurring during a first time interval representing the analog signal level, characterized by: means responsive to the termination of the first time interval and a time adjacent discrete event of the timing signal for generating a second time interval, said second time interval being a measure of the error between the analog signal level and the digital representation of the analog signal level; and means for effectively amplifying said second time interval by a predetermined factor.
Claim 8
Dependent Claim
112 words
In a multistage analog to digital converter wherein each stage generates a portion of a digital representation of an analog signal level, the portion being formed by means for counting discrete events of a timing signal occurring during a first time interval representing the analog signal level, characterized by: means responsive to the termination of the first time interval and a time adjacent discrete event of the timing signal for generating a second time interval, said second time interval being a measure of the error between the analog signal level and the digital representation of the analog signal level; and means for effectively amplifying said second time interval by a predetermined factor.
Claim 9
Dependent Claim
32 words
In a converter according to claim 6 wherein the predetermined factor is proportional to the highest possible number count of said one portion; whereby the amplification is inversely proportional to the resolution.
Claim 10
Dependent Claim
20 words
In a converter according to claim 6 wherein the amplifying means includes means for performing duration-to-amplitude conversion and amplitude-to-duration conversion.
Claim 11
Dependent Claim
37 words
In a converter according to claim 6 wherein the second time interval extends between the termination of the first time interval and the next discrete event of the timing signal to thereby form a complementary remainder signal.
References Cited (Backward Citations)
US3148366A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-12 | 1982-09-11 | 1983-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-12 | 1986-09-11 | 1987-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-12 | 1990-09-11 | 1991-03-13 | $7700.00 | Window Closed / Lapsed |