US4143327A
Expired / Lapsed
US
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Method and apparatus for generating tone signals and the like
Assignee: Kimball International Inc
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Filing: 1977-07-08
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Granted: 1979-03-06
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Expires: 1997-07-08
Abstract
Abstract A method and apparatus for generating tone signals and the like in which a given frequency is employed for controlling a counter arrangement at a frequency which is equal to the frequency of the given signal multiplied by a factor other than a whole number. The multiplied frequency output when divided down will yield a frequency differing a desired amount from the given frequency.
Inventors
- 👤 Alan B. Welsh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:55
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; G10; G10H; G10H5/00; G10H5/02; G10H5/06
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
170 words
A pulse generating circuit comprising: first binary counter means having a clock terminal and a clear terminal and a plurality of least significant bits output terminals and a plurality of most significant bits output terminals, second binary counter means having clock terminal means and load terminal means and output terminal means which pulses at a predetermined count in said second counter means and also having input terminal means for loading a count in said second counter means, latch means interposed between the input terminal means of said second counter means and the most significant bits output terminals of said first counter means, means for clocking said first and second counter means at a first higher frequency, first means for clocking said latch means at a second lower frequency, and second means for clearing said first counter means after clocking of said latch means, the frequency of the pulses at the output terminal means of said second counter means differing a small amount from a whole multiple of said second frequency.
Claim 2
Dependent Claim
170 words
A pulse generating circuit comprising: first binary counter means having a clock terminal and a clear terminal and a plurality of least significant bits output terminals and a plurality of most significant bits output terminals, second binary counter means having clock terminal means and load terminal means and output terminal means which pulses at a predetermined count in said second counter means and also having input terminal means for loading a count in said second counter means, latch means interposed between the input terminal means of said second counter means and the most significant bits output terminals of said first counter means, means for clocking said first and second counter means at a first higher frequency, first means for clocking said latch means at a second lower frequency, and second means for clearing said first counter means after clocking of said latch means, the frequency of the pulses at the output terminal means of said second counter means differing a small amount from a whole multiple of said second frequency.
Claim 3
Dependent Claim
25 words
A pulse generating circuit according to claim 1 which includes means for squaring the pulses from the output terminal means of said second counter means.
Claim 4
Dependent Claim
48 words
A pulse generating circuit according to claim 1 which includes means for squaring the pulse from the output terminal means of said second counter means and for dividing the frequency thereof to provide a pulse train having a frequency near but not equal to the said second frequency.
Claim 5
Dependent Claim
53 words
A pulse generating circuit according to claim 1 in which said second counter means comprises a pair of modulo counters each having an output terminal which pulses at a respective count in the pertaining counter, the pulse frequencies at the output terminals of said second counters differing a small amount from one another.
Claim 6
Dependent Claim
23 words
A pulse generating circuit according to claim 4 which includes means for squaring the pulses from the output(s) terminals of said modulo counters.
Claim 7
Dependent Claim
46 words
A pulse generating circuit according to claim 4 which includes means for squaring the pulses from the output terminals of said second modulo counters and for dividing the frequency thereof to provide pulse trains having frequencies near but different from said second frequency by respective amounts.
Claim 8
Dependent Claim
33 words
A pulse generating circuit according to claim 3 which includes a combining network in which said pulse train and said means for clocking said latch means are combined to form a single output.
Claim 9
Dependent Claim
33 words
A pulse generating circuit according to claim 6 which includes a combining network in which said pulse trains and said means for clocking said latch means are combined to form a single output.
Claim 10
Dependent Claim
25 words
A pulse generating circuit according to claim 1 in which said latch means inverts the signal at the output terminals of said first counter means.
Claim 11
Dependent Claim
18 words
The pulse generating circuit according to claim 1 wherein said second counter means is of the modulo type.
Claim 12
Dependent Claim
64 words
A pulse generating circuit according to claim 10 wherein the input terminal means of said second counter means are fewer in number than the combined output terminals of said first counter means, and said latch means is interposed between the input terminal means of said second counter means and the output terminals of said first counter means starting with the most significant bits terminals.
Claim 13
Dependent Claim
31 words
A pulse generating circuit according to claim 1 wherein said second means for clearing said first counter means clears said first counter means immediately after the clocking of said latch means.
Claim 14
Independent Claim
188 words
A method of generating a pulse train having a frequency which differs a predetermined amount from a whole multiple of a reference frequency which comprises: supplying clock pulses at a higher frequency and supplying further reference pulses at a frequency lower than said higher frequency, repetitively counting the number of clock pulses during a cycle of said reference frequency and representing the count in the form of a first binary word, transferring a predetermined number less than the total number of the bits of said first binary word commencing at the most significant end of the word to a place of storage to form a second binary word of smaller value than said first binary word, transferring said predetermined number of bits at the beginning of each cycle of the reference frequency, repetitively counting off at least one of: the second binary word and the binary compliment thereof, during the respective cycle of said reference frequency and generating a pulse at the end of each said counting off to form a pulse train having a frequency differing a small amount from a whole multiple of said reference frequency.
Claim 15
Independent Claim
188 words
A method of generating a pulse train having a frequency which differs a predetermined amount from a whole multiple of a reference frequency which comprises: supplying clock pulses at a higher frequency and supplying further reference pulses at a frequency lower than said higher frequency, repetitively counting the number of clock pulses during a cycle of said reference frequency and representing the count in the form of a first binary word, transferring a predetermined number less than the total number of the bits of said first binary word commencing at the most significant end of the word to a place of storage to form a second binary word of smaller value than said first binary word, transferring said predetermined number of bits at the beginning of each cycle of the reference frequency, repetitively counting off at least one of: the second binary word and the binary compliment thereof, during the respective cycle of said reference frequency and generating a pulse at the end of each said counting off to form a pulse train having a frequency differing a small amount from a whole multiple of said reference frequency.
Claim 16
Dependent Claim
18 words
The method according to claim 13 in which said transferred bits are inverted in said place of storage.
Claim 17
Dependent Claim
57 words
The method according to claim 14 which includes additionally counting off a binary word differing a small amount from said one of said second binary word and the complement thereof to generate additional pulses, and squaring said additional pulses to form a further pulse train differing in frequency a small amount from the other generated pulse train.
Claim 18
Dependent Claim
28 words
The method according to claim 13 which includes dividing the pulse train frequency down to produce pulses at a frequency differing a small amount from said reference frequency.
Claim 19
Dependent Claim
33 words
The method according to claim 13 which includes dividing both said pulse train frequencies down to produce pulses at frequencies which differ a small amount from each other and from said reference frequency.
Claim 20
Dependent Claim
19 words
The method according to claim 13 including squaring the pulses generated at the end of each said counting off.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-05 | 1982-09-04 | 1983-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-05 | 1986-09-04 | 1987-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-05 | 1990-09-04 | 1991-03-06 | $7700.00 | Window Closed / Lapsed |