Sequence controller with dynamically changeable program

Claim 2

For use in a process control system having processing apparatus to be sequenced, a sequence controller with a dynamically changeable sequencing program, including: a plurality of process-signal input terminals adapted for connection to selected and respective condition indicators in said process control system; an equal plurality of AND gates, each having a signal pin, a gating pin and an output pin, each of said process signal input terminals being connected to a respective one of said signal pins of said AND gates, said AND gates each being responsive to the coincidence of a process signal and a "one" gating signal at its signal and gating pins, respectively, to produce a stage-indication signal at its output terminal; read-only memory means having a plurality of multiple-step storage stages each containing, at each step, output signals comprising sequence control signals and associated binary gating signals, said gating signals being, in number, at least equal to the number of said AND gates, said read-only memory means having stage addressing pins, sequence-control-signal output pins and, in addition, a gating signal output terminal corresponding to each of said binary gating signals, each of said gating signal output terminals of said read-only memory being connected to a respective one of said gating pins of said AND gates; stage and step addressing and read-out means, including counter means, coupled between said output pins of said AND gates and said stage-addressing pins of said read-only memory and responsive to stage-indication signals from said AND gates for addressing and reading out, selectively, from stages and steps in said read-only memory the sequence control and gating signals contained therein; and, means coupled to said addressing and read-out means for applying said sequence control signals to said processing apparatus.

Claim 3

Apparatus according to claim 1 in which said read-only memory is programmable.

Claim 4

Apparatus according to claim 1 in which said stage and step addressing and read-out means includes a stage decision circuit coupled between said output pins of said AND gates and said stage-addressing pins of said read-only memory and responsive to stage-indication signals from a plurality of said AND gates for designating the stage-indication signal of highest priority for addressing said read-only memory.

Claim 5

Apparatus according to claim 3 in which said stage and step addressing and read-out means includes, in addition, control means coupled to said stage decision circuit and to said gating signal output terminals of said read-only memory and responsive to signals from said stage decision circuit and said gating signal output terminals for producing stage setting, counter stepping and register setting signals at its stage-setting, counter stepping and register-setting output terminals, respectively.

Claim 6

Apparatus according to claim 4 which includes, in addition, a buffer register having signal input terminals connected to said sequence-control-signal output pins of said read-only memory and a set pin coupled to said register-setting output terminal of said control means, and responsive to a register-setting signal from said control means to store sequence-control signals from said read-only memory for later controlling of said processing apparatus.

Claim 7

In a sequence controller for use in a process control system and having a plurality of signal input terminals adapted to have applied thereto related input signals from respective process condition indicators in said system, each such signal input terminal being coupled to a signal input pin of a respective AND gate, each such AND gate having also a gating pin and a stage indication signal output pin, each such output pin being coupled, selectively, through a priority-encoder to a respective one of the stage-addressing pins of a multiple stage, multiple step read-only memory the sequence-control signal output pins of which are connected to a buffer register; the method for providing a dynamically changeable program for such controller, which includes the steps of: storing at each step in each utilized stage of said read-only memory binary sequence control signals and an accompanying series of binary gating signals each of said binary gating signals in said series being intended for a respective and specific one of said AND gates, at least one of such binary signals being a "1" if priority is to be given to its related input signal on the appearance of that input signal at its signal input terminal; reading out said sequence control signals and said accompanying gating signals from successive steps in a first stage of said read-only memory; applying each of said gating signals to the gating pin of its intended AND gate; deriving a stage indication signal from the output pin of each intended AND gate upon the coincidence of gating and input signals at said gating and signal input pins, respectively, of each such intended AND gate; selectively utilizing said stage indication signal from one of said intended AND gates to address a second stage in said read-only memory for reading out therefrom a second set of sequence control signals and its accompanying series of gating signals; and, utilizing said first and second sets of sequence control signals to initiate first and second sequences in said process control system.

Claim 8

In a sequence controller for use in a process control system and having a plurality of signal input terminals adapted to have applied thereto related input signals from respective process condition indicators in said system, each such signal input terminal being coupled to a signal input pin of a respective AND gate, each such AND gate having also a gating pin and a stage indication signal output pin, each such output pin being coupled, selectively, through a priority-encoder to a respective one of the stage-addressing pins of a multiple stage, multiple step read-only memory the sequence-control signal output pins of which are connected to a buffer register; the method for providing a dynamically changeable program for such controller, which includes the steps of: storing at each step in each utilized stage of said read-only memory binary sequence control signals and an accompanying series of binary gating signals each of said binary gating signals in said series being intended for a respective and specific one of said AND gates, at least one of such binary signals being a "1" if priority is to be given to its related input signal on the appearance of that input signal at its signal input terminal; reading out said sequence control signals and said accompanying gating signals from successive steps in a first stage of said read-only memory; applying each of said gating signals to the gating pin of its intended AND gate; deriving a stage indication signal from the output pin of each intended AND gate upon the coincidence of gating and input signals at said gating and signal input pins, respectively, of each such intended AND gate; selectively utilizing said stage indication signal from one of said intended AND gates to address a second stage in said read-only memory for reading out therefrom a second set of sequence control signals and its accompanying series of gating signals; and, utilizing said first and second sets of sequence control signals to initiate first and second sequences in said process control system.

Claim 9

The method according to claim 6 which includes the additional step of priority-encoding any stage indication signal from each of said AND gates.

Claim 10

The method according to claim 6 which includes the additional step of storing said sequence control signals, only, read out from said read-only memory, prior to the step of utilizing any part of either of such first and second sets of sequence control signals.