Harmonic insensitive phase sensitive demodulator

Claim 2

A phase sensitive demodulator responsive to a reference signal having a frequency w and to an input signal comprising: (a) means for synthesizing from said reference signal a sinusoidal function having a Fourier series substantially of the form sin ##EQU2## being an odd number and at least 7; and (b) means for digitally multiplying said function and said input signal so as to render the demodulator output substantially insensitive to the nth and lower odd harmonics of w present in the input signal.

Claim 3

The phase sensitive demodulator of claim 1 wherein n is an odd number and at least 13.

Claim 4

The phase sensitive demodulator of claim 1 wherein n is an odd number and at least 29.

Claim 5

The phase sensitive demodulator of claim 1 wherein said synthesizing means comprises a phase locked loop.

Claim 6

The phase sensitive demodulator of claim 4 wherein said phase locked loop comprises: (a) a demodulator having as one input said reference signal; (b) a voltage controlled oscillator connected to the output of said deomodulator, said oscillator oscillating at a frequency of at least (n+3)w; and (c) counter means connected to the output of said voltage controlled oscillator and to said demodulator for dividing the output frequency of said oscillator down to the frequency w and providing switching signals for said demodulator.

Claim 7

A phase sensitive demodulator sensitive to a reference signal having a frequency w and to an input signal comprising: (a) phase locked loop means for synthesizing from said reference a sinusoidal function having a Fourier series substantially of the form sin ##EQU3## n being an odd number and at least 7; and (b) means for digitally multiplying said function and said input signal so as to render the demodulator output substantially insensitive to the nth and lower odd harmonics of w present in the input signal, said digital multiplying means comprising a switched resistive network, said resistive network being weighted trigonometrically.

Claim 8

A phase sensitive demodulator sensitive to a reference signal having a frequency w and to an input signal comprising: (a) phase locked loop means for synthesizing from said reference a sinusoidal function having a Fourier series substantially of the form sin ##EQU3## n being an odd number and at least 7; and (b) means for digitally multiplying said function and said input signal so as to render the demodulator output substantially insensitive to the nth and lower odd harmonics of w present in the input signal, said digital multiplying means comprising a switched resistive network, said resistive network being weighted trigonometrically.

Claim 9

The phase sensitive demodulator of claim 6 wherein said phase locked loop comprises: (a) a demodulator having as one input said reference signal; (b) a voltage controlled oscillator connected to the output of said demodulator, said oscillator oscillating at a frequency of at least (n+3)w; (c) counter means connected to the output of said voltage controlled oscillator and to said demodulator for dividing the output frequency of said oscillator down to the frequency w and providing switching signals for said demodulator.

Claim 10

The phase sensitive demodulator of claim 6 wherein said phase locked loop comprises: (a) a digital multiplier having as one input said reference signal; (b) a voltage controlled oscillator connected to the output of said digital multiplier, said oscillator oscillating at a frequency of at least (n+3)w; (c) counter means connected to the output of said voltage controlled oscillator for dividing the output frequency of said oscillator down to the frequency w; (d) logic means connected to the outputs of said counter means and to the other input of said digital multiplier to switch said multiplier every 360/n+3 degrees so as to render the phase locked loop substantially insensitive to the nth and lower odd harmonics present in the reference signal.

Claim 11

A phase sensitive demodulator responsive to a reference signal having a frequency w and to an input signal comprising: (a) phase locked loop means for synthesizing from said reference a sinusoidal function having a Fourier series substantially of the form sin ##EQU4## n being an odd number and at least 7; (b) means for digitally multiplying said reference signal and said sinusoidal function so as to render the demodulator output subtantially insensitive to the nth and lower odd harmonics of w present in the input signal, said digital multiplying means comprising a sine read only memory and a multiplying linear digital-analog converter connected thereto.

Claim 12

A phase sensitive demodulator responsive to a reference signal having a frequency w and to an input signal comprising: (a) phase locked loop means for synthesizing from said reference a sinusoidal function having a Fourier series substantially of the form sin ##EQU4## n being an odd number and at least 7; (b) means for digitally multiplying said reference signal and said sinusoidal function so as to render the demodulator output subtantially insensitive to the nth and lower odd harmonics of w present in the input signal, said digital multiplying means comprising a sine read only memory and a multiplying linear digital-analog converter connected thereto.

Claim 13

The phase sensitive demodulator of claim 9 wherein said phase locked loop comprises: (a) a demodulator having as one input said reference signal; (b) a voltage controlled oscillator connected to the output of said demodulator, said oscillator oscillating at a frequency of at least (n+3)w; and (c) counter means connected to the output of said voltage controlled oscillator and to said demodulator for dividing the output frequency of said oscillator down to w and providing switching signals for said demodulator.

Claim 14

The phase sensitive demodulator of claim 9 wherein said phase locked loop comprises: (a) a digital multiplier having as one input said reference signal; (b) a voltage controlled oscillator connected to the output of said digital multiplier, said oscillator oscillating at a frequency of at least (n+3)w; (c) counter means connected to the output of said voltage controlled oscillator for dividing the output frequency of said oscillator down to the frequency w; (d) logic means connected to the outputs of said counter means and to the other input of said digital multiplier to switch said multiplier every 360/n+3 degrees so as to render the phase locked loop substantially insensitive to the nth and lower odd harmonics present in the reference signal.

Claim 15

The phase sensitive demodulator of claim 11 wherein n is an odd number and at least 29.

Claim 18

The method of claim 13 wherein the synthesizing step comprises the steps of: (a) generating an intermediate signal having a frequency of at least (n+3)w; (b) dividing the frequency of said intermediate signal down to w; and (c) demodulating the reference signal.