Inverter with improved load line characteristic

Claim 1

A method for fabricating an enhancement/depletion mode IGFET inverter circuit having an improved load current characteristic in a substrate of a first conductivity type, comprising the steps of: forming a masking layer on the surface of said substrate; opening a window in said masking layer defining an area for the location of a depletion mode IGFET device; anisotropically etching a flat bottom well through said window; depositing and driving in a second conductivity type dopant to form a PN junction completely surrounding said well; depositing a first conductivity type epitaxial layer to refill said well coplanar with the original substrate surface; masking to define an area within the bounds of said well; removing said masking layer outside the area of said well, defining a frame between the remaining masking layer on top of the refilled well and the edges of said window; etching an isolation moat in said frame; forming an insulating layer to fill said etched isolation moat; diffusing a first source and drain regions of said second conductivity type in said refilled well forming a load device and a second source and drain regions of said second conductivity type in said substrate forming an active device; defining gate regions between said first source and drain; forming an insulating layer in said gate regions for the gate dielectric; ion-implanting a channel region of said second conductivity type for said load device to form a depletion mode load device; defining metal gate shapes and patterns connecting the gate, source and substrate of said load device to the drain of said active device; whereby an enhancement/depletion mode IGFET circuit configuration with improved current driving capabilities is formed.

Claim 2

A method for fabricating an enhancement/depletion mode IGFET inverter circuit having an improved load current characteristic in a substrate of a first conductivity type, comprising the steps of: forming a masking layer on the surface of said substrate; opening a window in said masking layer defining an area for the location of a depletion mode IGFET device; anisotropically etching a flat bottom well through said window; depositing and driving in a second conductivity type dopant to form a PN junction completely surrounding said well; depositing a first conductivity type epitaxial layer to refill said well coplanar with the original substrate surface; masking to define an area within the bounds of said well; removing said masking layer outside the area of said well, defining a frame between the remaining masking layer on top of the refilled well and the edges of said window; etching an isolation moat in said frame; forming an insulating layer to fill said etched isolation moat; diffusing a first source and drain regions of said second conductivity type in said refilled well forming a load device and a second source and drain regions of said second conductivity type in said substrate forming an active device; defining gate regions between said first source and drain; forming an insulating layer in said gate regions for the gate dielectric; ion-implanting a channel region of said second conductivity type for said load device to form a depletion mode load device; defining metal gate shapes and patterns connecting the gate, source and substrate of said load device to the drain of said active device; whereby an enhancement/depletion mode IGFET circuit configuration with improved current driving capabilities is formed.

Claim 3

A method for fabricating an N-channel enhancement/depletion mode IGFET inverter circuit having an improved load current characteristic in a P type substrate, comprising the steps of: growing a layer of thermal silicon dioxide on the surface of said substrate followed by the deposition of a layer of silicon nitride; opening a window defining the area for the location of a depletion mode IGFET device; anisotropically etching a flat bottom well through said window; depositing and driving in an N type dopant to form a PN junction completely surrounding said well; depositing a P type epitaxial silicon layer to refill said well coplanar with the original substrate surface; masking to define an area within the bounds of said P well; etching said silicon nitride and silicon dioxide layers outside the area of said well defining a frame between the remaining nitride and oxide on top of the P refilled well and the edges of said window; removing the polycrystalline silicon layer lying on top of the field regions outside of said P well and etching an isolation moat in said frame; growing a thermal silicon dioxide layer to fill said isolation moat; dip etching remaining nitride layer on top of P type well; diffusing first N type source and drain regions in said well forming a load device and second N type source and drain regions in said substrate forming an active device; defining gate regions between said first source and drain and said second source and drain; growing a thermal silicon dioxide layer in said gate regions for the gate dielectric; ion-implanting an N-channel for said load device to form a depletion mode load device; defining metal gate shapes and patterns to interconnect the gate, source and substrate of said load device to the drain of said active device; whereby an enhancement/depletion mode IGFET circuit configuration with improved current driving capabilities is formed.

Claim 4

A method for fabricating an N-channel enhancement/depletion mode IGFET inverter circuit having an improved load current characteristic in a P type substrate, comprising the steps of: growing a layer of thermal silicon dioxide on the surface of said substrate followed by the deposition of a layer of silicon nitride; opening a window defining the area for the location of a depletion mode IGFET device; anisotropically etching a flat bottom well through said window; depositing and driving in an N type dopant to form a PN junction completely surrounding said well; depositing a P type epitaxial silicon layer to refill said well coplanar with the original substrate surface; masking to define an area within the bounds of said P well; etching said silicon nitride and silicon dioxide layers outside the area of said well defining a frame between the remaining nitride and oxide on top of the P refilled well and the edges of said window; removing the polycrystalline silicon layer lying on top of the field regions outside of said P well and etching an isolation moat in said frame; growing a thermal silicon dioxide layer to fill said isolation moat; dip etching remaining nitride layer on top of P type well; diffusing first N type source and drain regions in said well forming a load device and second N type source and drain regions in said substrate forming an active device; defining gate regions between said first source and drain and said second source and drain; growing a thermal silicon dioxide layer in said gate regions for the gate dielectric; ion-implanting an N-channel for said load device to form a depletion mode load device; defining metal gate shapes and patterns to interconnect the gate, source and substrate of said load device to the drain of said active device; whereby an enhancement/depletion mode IGFET circuit configuration with improved current driving capabilities is formed.

Claim 5

A method for simultaneously fabricating an enhancement/depletion mode IGFET inverter circuit having an improved load current characteristic and a bipolar transistor in a first conductivity type substrate, comprising the steps of: forming a masking layer on the surface of said substrate; opening a first window in said masking layer defining the area for the location of a depletion mode IGFET device and a second window defining the area for the location of a bipolar transistor; anisotropically etching a first flat bottom well through said first window and a second flat bottom well through said second window; depositing and driving in a second conductivity type dopant to form a PN junction completely surrounding said first well and to form the collector for said bipolar transistor in said second well; depositing a first conductivity type epitaxial layer to refill each of said wells coplanar with the original substrate surface, forming the base for said bipolar transistor in said second well; masking to define an area within the bounds of said first and second wells; removing said masking layer outside the area of each of said wells defining a frame between the remaining masking layer on top of each of said refilled wells and the edges of said respective windows; etching isolation moats in each of said frames; forming insulating layers to fill each of said isolating moats; dip etching remaining masking layer on top of refilled wells; diffusing first source and drain regions of said second conductivity type in said first well forming a load device, second source and drain regions of said second conductivity type in said substrate forming an active device, and an emitter region in said second well; defining gate regions between said first source and drain and forming an insulating layer in said gate region for the gate dielectric; ion-implanting a channel region of said second conductivity type for the load device to form a depletion mode load device; defining metal gate shapes and patterns to interconnect the gate, source and substrate of said load device to the drain of said active device; whereby an enhancement/depletion mode IGFET circuit configuration with improved current driving capabilities is formed simultaneously with the formation of a bipolar transistor.

Claim 6

A method for simultaneously fabricating an enhancement/depletion mode IGFET inverter circuit having an improved load current characteristic and a bipolar transistor in a first conductivity type substrate, comprising the steps of: forming a masking layer on the surface of said substrate; opening a first window in said masking layer defining the area for the location of a depletion mode IGFET device and a second window defining the area for the location of a bipolar transistor; anisotropically etching a first flat bottom well through said first window and a second flat bottom well through said second window; depositing and driving in a second conductivity type dopant to form a PN junction completely surrounding said first well and to form the collector for said bipolar transistor in said second well; depositing a first conductivity type epitaxial layer to refill each of said wells coplanar with the original substrate surface, forming the base for said bipolar transistor in said second well; masking to define an area within the bounds of said first and second wells; removing said masking layer outside the area of each of said wells defining a frame between the remaining masking layer on top of each of said refilled wells and the edges of said respective windows; etching isolation moats in each of said frames; forming insulating layers to fill each of said isolating moats; dip etching remaining masking layer on top of refilled wells; diffusing first source and drain regions of said second conductivity type in said first well forming a load device, second source and drain regions of said second conductivity type in said substrate forming an active device, and an emitter region in said second well; defining gate regions between said first source and drain and forming an insulating layer in said gate region for the gate dielectric; ion-implanting a channel region of said second conductivity type for the load device to form a depletion mode load device; defining metal gate shapes and patterns to interconnect the gate, source and substrate of said load device to the drain of said active device; whereby an enhancement/depletion mode IGFET circuit configuration with improved current driving capabilities is formed simultaneously with the formation of a bipolar transistor.

Claim 7

A method for simultaneously fabricating an enhancement/depletion mode IGFET inverter circuit having an improved load current characteristic and an NPN bipolar transistor in a P type substrate, comprising the steps of: growing a layer of thermal silicon dioxide on the surface of said substrate followed by the deposition of a layer of silicon nitride; opening a first window defining the area for the location of a depletion mode IGFET device and a second window defining the area for the location of an NPN bipolar transistor; anisotropically etching a first flat bottom well through said first window and a second flat bottom well through said second window; depositing and driving in an N type dopant to form a PN junction completely surrounding said first well and to form the collector for said bipolar transistor in said second well; depositing a P type epitaxial silicon layer to refill each said well coplanar with the original substrate surface, forming the base for said bipolar transistor in said second well; masking to define an area within the bounds of said first and second wells; etching said silicon nitride and silicon oxide layers outside the area of each said well, defining a frame between the remaining nitride and oxide on top of each of said refilled wells and the edges of said respective windows; removing the polycrystalline silicon layer lying on top of the field regions outside of each said well and etching isolation moats in each of said frames; growing thermal silicon dioxide layers to fill each of said isolation moats; dip etching silicon nitride layer remaining on top of P type wells; diffusing first N type source and drain regions in said first well forming a load device, second N type source and drain regions in said substrate forming an active device, and an N type emitter region in said second well; defining gate regions between said first source and drain and said second source and drain; growing a thermal silicon dioxide layer in said gate regions for the gate dielectric; ion-planting an N-channel for the load device to form a depletion mode load device; defining metal gate shapes and patterns to interconnect the gate, source and substrate of said load device to the drain of said active device; whereby an enhancement/depletion mode IGFET circuit configuration with improved current driving capabilities is formed simultaneously with the formation of an NPN bipolar transistor.

Claim 8

A method for simultaneously fabricating an enhancement/depletion mode IGFET inverter circuit having an improved load current characteristic and an NPN bipolar transistor in a P type substrate, comprising the steps of: growing a layer of thermal silicon dioxide on the surface of said substrate followed by the deposition of a layer of silicon nitride; opening a first window defining the area for the location of a depletion mode IGFET device and a second window defining the area for the location of an NPN bipolar transistor; anisotropically etching a first flat bottom well through said first window and a second flat bottom well through said second window; depositing and driving in an N type dopant to form a PN junction completely surrounding said first well and to form the collector for said bipolar transistor in said second well; depositing a P type epitaxial silicon layer to refill each said well coplanar with the original substrate surface, forming the base for said bipolar transistor in said second well; masking to define an area within the bounds of said first and second wells; etching said silicon nitride and silicon oxide layers outside the area of each said well, defining a frame between the remaining nitride and oxide on top of each of said refilled wells and the edges of said respective windows; removing the polycrystalline silicon layer lying on top of the field regions outside of each said well and etching isolation moats in each of said frames; growing thermal silicon dioxide layers to fill each of said isolation moats; dip etching silicon nitride layer remaining on top of P type wells; diffusing first N type source and drain regions in said first well forming a load device, second N type source and drain regions in said substrate forming an active device, and an N type emitter region in said second well; defining gate regions between said first source and drain and said second source and drain; growing a thermal silicon dioxide layer in said gate regions for the gate dielectric; ion-planting an N-channel for the load device to form a depletion mode load device; defining metal gate shapes and patterns to interconnect the gate, source and substrate of said load device to the drain of said active device; whereby an enhancement/depletion mode IGFET circuit configuration with improved current driving capabilities is formed simultaneously with the formation of an NPN bipolar transistor.