← Back to Patent Explorer
US4138665A Expired / Lapsed US ⏱️ 0.0 years remaining

Preamplifier for analog to digital converters

Assignee: General Electric Co
•
Filing: 1977-09-21
•
Granted: 1979-02-06
•
Expires: 1997-09-21
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A preamplifier using charge transfer techniques is formed on the same chip as a charge transfer analog to digital converter. The preamplifier then couples low level output sensors directly to the converter without need for a costly interfacing amplifier.

Inventors

  • 👤 Charles W. Eichelberger
  • 👤 Walter J. Butler

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 05:25
CPC Classifications
H; H05; H05K; H05K13/00; H05K13/02; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/52

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 176 words
An amplifier circuit comprising, in combination: a first capacitor having a capacitance C; a second capacitor having a capacitance kC; input circuit means including a pair of switching transistors for sequentially connecting the opposite polarities of an input signal to said second capacitor to change the voltage applied to said second capacitor by an input voltage V i ; output circuit means connected to said first capacitor; and charge transfer transistor circuit means for transferring charge from said second capacitor to said first capacitor to produce an output voltage kV i on said output circuit means in response to a change of voltage V i on said second capacitor, and including a transistor adapted to operate in a "shelf" mode and connected between said first and second capacitors, whereby said charge transfer transistor circuit means becomes conducting when the voltage across said second capacitor changes by V i to transfer a charge packet having a magnitude q i =kCV i to said first capacitor to increase the voltage across said first capacitor by kV i .
Claim 2
Dependent Claim 176 words
An amplifier circuit comprising, in combination: a first capacitor having a capacitance C; a second capacitor having a capacitance kC; input circuit means including a pair of switching transistors for sequentially connecting the opposite polarities of an input signal to said second capacitor to change the voltage applied to said second capacitor by an input voltage V i ; output circuit means connected to said first capacitor; and charge transfer transistor circuit means for transferring charge from said second capacitor to said first capacitor to produce an output voltage kV i on said output circuit means in response to a change of voltage V i on said second capacitor, and including a transistor adapted to operate in a "shelf" mode and connected between said first and second capacitors, whereby said charge transfer transistor circuit means becomes conducting when the voltage across said second capacitor changes by V i to transfer a charge packet having a magnitude q i =kCV i to said first capacitor to increase the voltage across said first capacitor by kV i .
Claim 3
Dependent Claim 11 words
The circuit of claim 1, wherein k is greater than 1.
Claim 4
Dependent Claim 14 words
The circuit of claim 1, wherein said transistor circuit means consists of MOSFET-type transistors.
Claim 5
Dependent Claim 24 words
The circuit of claim 1, which further includes a second switching transistor means for connecting one terminal of said second capacitor to zero potential.
Claim 6
Dependent Claim 12 words
The circuit of claim 4, wherein k is substantially greater than 1.
Claim 7
Dependent Claim 15 words
The circuit of claim 5, wherein all of said transistors are of the MOSFET type.
Claim 8
Dependent Claim 257 words
An analog to digital converter for use with a low level sensor which produces a relatively low analog output signal voltage V i , said analog to digital converter comprising: charge-transfer means for converting an analog signal at an analog input circuit to a digital representative of said analog signal at a digital output circuit; and a preamplifier connected between said low level sensor and said analog input circuit to sufficiently preamplify said analog output signal voltage to produce a desired bit resolution from said digital output circuit; said preamplifier circuit comprising, in combination: a first capacitor having a capacitance C; a second capacitor having a capacitance kC; first means comprising a pair of switching transistors each connected between a first terminal of said second capacitor and a different side of the output of said low voltage sensor for connecting said output voltage V i to said second capacitor to change the voltage across said second capacitor by said voltage V i ; transistor switching means for connecting said first capacitor to said second capacitor to permit current to flow between said first and second capacitors when said switching transistor means is conducting and causing, after the voltage across said second capacitor is changed by V i , a charge packet q 1 - kCV i to be transferred to said first capacitor to increase the voltage across said first capacitor by kV i ; and second means for connecting the voltage across said first capacitor to said analog input circuit of said charge transfer converting means.
Claim 9
Dependent Claim 257 words
An analog to digital converter for use with a low level sensor which produces a relatively low analog output signal voltage V i , said analog to digital converter comprising: charge-transfer means for converting an analog signal at an analog input circuit to a digital representative of said analog signal at a digital output circuit; and a preamplifier connected between said low level sensor and said analog input circuit to sufficiently preamplify said analog output signal voltage to produce a desired bit resolution from said digital output circuit; said preamplifier circuit comprising, in combination: a first capacitor having a capacitance C; a second capacitor having a capacitance kC; first means comprising a pair of switching transistors each connected between a first terminal of said second capacitor and a different side of the output of said low voltage sensor for connecting said output voltage V i to said second capacitor to change the voltage across said second capacitor by said voltage V i ; transistor switching means for connecting said first capacitor to said second capacitor to permit current to flow between said first and second capacitors when said switching transistor means is conducting and causing, after the voltage across said second capacitor is changed by V i , a charge packet q 1 - kCV i to be transferred to said first capacitor to increase the voltage across said first capacitor by kV i ; and second means for connecting the voltage across said first capacitor to said analog input circuit of said charge transfer converting means.
Claim 10
Dependent Claim 11 words
The circuit of claim 7, wherein k is greater than 1.
Claim 11
Dependent Claim 18 words
The circuit of claim 7, wherein k is in the range of from about 10 to about 200.
Claim 12
Dependent Claim 48 words
The circuit of claim 7, wherein said transistor switching means is a shelf transistor having a fixed negative gate voltage and which further includes second transistor switching means connected to said first transistor and to said first capacitor for applying a biasing voltage to said first transistor means.
Claim 13
Dependent Claim 32 words
The circuit of claim 7, which further includes a scaling transistor switching circuit means connected to said second capacitor for changing the scale of the digital output signal voltage V i .
Claim 14
Dependent Claim 25 words
The circuit of claim 7, wherein said preamplifier and said change transfer analog to digital converting means include MOSFET transistors formed on a common chip.
Claim 15
Dependent Claim 15 words
The circuit of claim 7, wherein said second means includes source follower transistor circuit means.

References Cited (Backward Citations)

US4051469A Cited
US4070667A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1982-02-05 1982-08-07 1983-02-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1986-02-05 1986-08-07 1987-02-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1990-02-05 1990-08-07 1991-02-06 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag