US4137504A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital filter
Assignee: Quantum Corp
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Filing: 1977-08-12
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Granted: 1979-01-30
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Expires: 1997-08-12
Abstract
Abstract A circuit for filtering electrical waveforms in which the useful information is contained in patterns and spacing of zero-voltage crossings is disclosed. Illustratively, a disk memory system is disclosed in which the voltage peaks developed by the disk memory read-transducers are converted into zero-voltage crossing waveforms by differentiation. To eliminate false zero-voltage crossings caused by noise, the digital filter generates a linear ramp waveform whose magnitude is proportional to the time duration between successive zero-voltage crossings. False zero crossings typically have a short time duration between successive crossings. They are eliminated from the integrated ramp waveform by a comparator which only responds when the integrated waveform reaches a predetermined threshold level indicating the time between successive zero-voltage crossing exceeds a minimum time duration. A balanced version of the digital filter circuitry is also disclosed which recovers a limited, filtered version of the original zero-voltage crossing wave form except for a slight delay.
Inventors
- 👤 Elmer C. Simmons
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:57
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
327 words
A filter circuit for electrically processing a voltage waveform having positive and negative portions, wherein information is contained in the pattern and spacing of zero-voltage crossings, to eliminate false zero crossings caused by noise, said circuit comprising; a. a first voltage comparator having positive and negative inputs, said first comparator producing an output when a voltage present at said positive input exceeds a voltage present at said negative input; b. means for connecting said voltage waveform to said positive input of said first comparator; c. means for connecting the inverse of said voltage waveform to said negative input of said first comparator means; d. a second voltage comparator having a positive and negative input, said second comparator producing an output when a voltage present at said positive input exceeds a voltage present at said negative input; e. means for connecting said voltage waveform to said negative input of said second comparator; f. means for connecting the inverse of said voltage waveform to said positive input of said second comparator; g. first integration means responsive to an output produced by said first comparator for generating a linearly increasing voltage waveform; h. second integration means responsive to the output of said second comparator for producing a linearly increasing voltage waveform; i. a reference voltage source; j. a third voltage comparator having a positive and negative input and an output, said positive input being connected to the output of said first integration means, and said negative input being connected to said reference voltage source; k. a fourth voltage comparator having a positive and negative input and an output, said positive input being connected to the output of said second integration means, and said negative input being connected to said reference voltage source; and l. a set-reset flip-flop having a set input and a reset input, said set input being connected to said output of said third comparator and said reset input being connected to said output of said fourth comparator.
Claim 2
Dependent Claim
327 words
A filter circuit for electrically processing a voltage waveform having positive and negative portions, wherein information is contained in the pattern and spacing of zero-voltage crossings, to eliminate false zero crossings caused by noise, said circuit comprising; a. a first voltage comparator having positive and negative inputs, said first comparator producing an output when a voltage present at said positive input exceeds a voltage present at said negative input; b. means for connecting said voltage waveform to said positive input of said first comparator; c. means for connecting the inverse of said voltage waveform to said negative input of said first comparator means; d. a second voltage comparator having a positive and negative input, said second comparator producing an output when a voltage present at said positive input exceeds a voltage present at said negative input; e. means for connecting said voltage waveform to said negative input of said second comparator; f. means for connecting the inverse of said voltage waveform to said positive input of said second comparator; g. first integration means responsive to an output produced by said first comparator for generating a linearly increasing voltage waveform; h. second integration means responsive to the output of said second comparator for producing a linearly increasing voltage waveform; i. a reference voltage source; j. a third voltage comparator having a positive and negative input and an output, said positive input being connected to the output of said first integration means, and said negative input being connected to said reference voltage source; k. a fourth voltage comparator having a positive and negative input and an output, said positive input being connected to the output of said second integration means, and said negative input being connected to said reference voltage source; and l. a set-reset flip-flop having a set input and a reset input, said set input being connected to said output of said third comparator and said reset input being connected to said output of said fourth comparator.
Claim 3
Dependent Claim
71 words
A filter circuit according to claim number 1 wherein said first integration means comprises; m. an open-collectored buffer inverter having an output and responsive to the output of said first comparator for inverting such output of said first comparator, n. integration voltage source, o. a resistor connecting said output of said buffer inverter to said integration voltage source, and p. a capacitor connecting said output of said buffer inverter to ground.
Claim 4
Dependent Claim
37 words
A filter circuit according to claim 2 further comprising; q. means for clamping the output of said first and second integration means to a predetermined voltage value to prevent overloading of said third and said fourth comparators.
Claim 5
Dependent Claim
30 words
A filter circuit according to claim 3 further comprising; r. means for correcting said reference voltage source for voltage offsets developed by said buffer inverter and said first integration means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-01-29 | 1982-07-31 | 1983-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-01-29 | 1986-07-31 | 1987-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-01-29 | 1990-07-31 | 1991-01-30 | $7700.00 | Window Closed / Lapsed |