Electronic delay detonator

Claim 2

An electronic delay detonator fired by a trigger signal comprising: a safety circuit with output current for arming the detonator; a current regulator electrically connected to said safety circuit output for limiting the current from the safety circuit output so as to produce a current output from said current regulator which cannot cause overloads; a power storage circuit which inputs said current regulator output for holding in reserve the energy delivered by said regulated current; a power-up reset circuit which receives as input the output of the current regulator for providing an initial timing signal; a trigger circuit connected to the power-up reset circuit and has said trigger signal as an input so as to initiate a predetermined fire delay timing period by an output from said trigger circuit; a fuse placed so as to ground the trigger circuit until a predetermined minimum trigger signal is received; a time delay circuit which receives the trigger circuit output for causing said fire delay timing period and outputting a signal when said predetermined delay time has passed; a firing circuit which is activated by the output of the time delay circuit and connected to said power storage circuit for releasing said energy reserve in said power storage circuit; and a detonator which receives said released energy for firing said detonator.

Claim 3

An electronic delay detonator as described in claim 1 where the safety circuit contains a diode to prevent reverse current flow.

Claim 4

An electronic delay detonator as described in claim 1 where the fuse is a bridgewire.

Claim 5

An electronic delay detonator as described in claim 1 where the time delay circuit is a 4013 dual CMOS D flip-flop.

Claim 6

An electronic delay detonator as described in claim 1 where the power storage circuit becomes the firing circuit upon the closing of a silicon controlled rectifier by the output of the time delay circuit.

Claim 7

An electronic delay detonator as described in claim 2 where the time delay circuit is a 4013 dual CMOS D flip-flop.

Claim 8

An electronic delay detonator as described in claim 3 where the time delay circuit is a 4013 dual CMOS D flip-flop.

Claim 9

An electronic delay detonator as described in claim 2 where the power storage circuit becomes the firing circuit upon the closing of a silicon controlled rectifier by the output of the time delay circuit.

Claim 10

An electronic delay detonator as described in claim 3 where the power storage circuit becomes the firing circuit upon the closing of a silicon controlled rectifier by the output of the time delay circuit.

Claim 11

An electronic delay detonator as described in claim 4 where the power storage circuit becomes the firing circuit upon the closing of a silicon controlled rectifier by the output of the time delay circuit.

Claim 12

An electronic delay detonator fired by a trigger signal comprising: a safety circuit with output current for arming said detonator wherein said safety circuit contains a diode to prevent reverse current flow; a current regulator electrically connected to said safety circuit output for limiting the current from the safety circuit output so as to produce a current output from said current regulator which cannot cause overloads; a power storage circuit which inputs said current regulator output for holding in reserve the energy delivered by said regulated current; a power-up reset circuit which receives as input the output of the current regulator for providing an initial timing signal; a trigger circuit connected to the power-up reset circuit and has said trigger signal as an input so as to initiate a predetermined fire delay timing period by an output from said trigger current; a bridgewire fuse placed so as to ground said trigger circuit until a predetermined minimum trigger signal is received; a 4013 dual CMOS D flip-flop time delay cirucit which receives said trigger circuit output for causing said fire delay timing period and outputting a signal when said predetermined delay time has passed; a firing circuit which is activated by the output of the time delay circuit and connected to said power storage circuit for releasing said energy reserve in said power storage circuit; and a detonator which receives said released energy for firing said detonator.

Claim 13

An electronic delay detonator fired by a trigger signal comprising: a safety circuit with output current for arming said detonator wherein said safety circuit contains a diode to prevent reverse current flow; a current regulator electrically connected to said safety circuit output for limiting the current from the safety circuit output so as to produce a current output from said current regulator which cannot cause overloads; a power storage circuit which inputs said current regulator output for holding in reserve the energy delivered by said regulated current; a power-up reset circuit which receives as input the output of the current regulator for providing an initial timing signal; a trigger circuit connected to the power-up reset circuit and has said trigger signal as an input so as to initiate a predetermined fire delay timing period by an output from said trigger current; a bridgewire fuse placed so as to ground said trigger circuit until a predetermined minimum trigger signal is received; a 4013 dual CMOS D flip-flop time delay cirucit which receives said trigger circuit output for causing said fire delay timing period and outputting a signal when said predetermined delay time has passed; a firing circuit which is activated by the output of the time delay circuit and connected to said power storage circuit for releasing said energy reserve in said power storage circuit; and a detonator which receives said released energy for firing said detonator.

Claim 14

An electronic delay detonator as described in claim 11 where the power storage circuit becomes the firing circuit upon the closing of a silicon controlled rectifier by the output of the time delay circuit.