US4136349A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ic chip with buried zener diode
Assignee: Analog Devices Inc
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Filing: 1977-05-27
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Granted: 1979-01-23
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Expires: 1997-05-27
Abstract
Abstract An IC chip having a Zener diode with a subsurface breakdown junction to assure stable operation. The diode is formed by a triple diffusion process compatible with conventional bipolar processing. A deep p ++ diffusion first is applied, reaching through the epitaxial region to the buried n + layer; next, a shallow p + diffusion is formed over the deep p ++ diffusion and extending laterally beyond that diffusion; finally, a shallow n + diffusion is applied over the p diffusions, to form a subsurface breakdown junction therewith. The topology of the mask windows is selected to provide concentration profiles which insure that the breakdown occurs at the subsurface junction, and that other desirable diode characteristics are achieved.
Inventors
- 👤 Wei K. Tsang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:30
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/20; H10D8/25
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
99 words
An IC chip comprising a planar element having a Zener diode junction formed of the following overlying set of diffusions: (a) a deep p diffusion; (b) a shallow p diffusion over said deep diffusion and having at least one side edge which is laterally beyond the corresponding side edge of said deep diffusion in one plane perpendicular to the surface of said element; and (c) an n diffusion over said shallow p diffusion, said n diffusion being shallower than said shallow p diffusion and positioned wholly within the lateral limits of said deep p diffusion in said one plane.
Claim 2
Dependent Claim
99 words
An IC chip comprising a planar element having a Zener diode junction formed of the following overlying set of diffusions: (a) a deep p diffusion; (b) a shallow p diffusion over said deep diffusion and having at least one side edge which is laterally beyond the corresponding side edge of said deep diffusion in one plane perpendicular to the surface of said element; and (c) an n diffusion over said shallow p diffusion, said n diffusion being shallower than said shallow p diffusion and positioned wholly within the lateral limits of said deep p diffusion in said one plane.
Claim 3
Dependent Claim
49 words
An IC chip as in claim 1, wherein the concentration of p dopant in the central region of the interface between said n diffusion and the p diffusion therebeneath is greater than the concentration of p dopant at the surface junction between the n diffusion and the p diffusion.
Claim 4
Dependent Claim
28 words
An IC chip as in claim 1, wherein said shallow p diffusion extends laterally substantially beyond said deep p diffusion on both sides thereof in said perpendicular plane.
Claim 5
Dependent Claim
43 words
An IC chip as in claim 3, wherein said shallow n diffusion, in a plane which is perpendicular both to the surface and said element and to said first-named plane, extends beyond the adjacent outer side edges of both of said p diffusions.
Claim 6
Dependent Claim
143 words
An IC chip presenting a buried Zener-diode junction comprising: a first layer of n dopant in the surface of the silicon layer of the chip; a second layer of p dopant having a first portion beneath said first layer and providing in its central regions a subsurface junction with said first layer; said second layer having a second portion extending out laterally beyond said first layer up to the silicon surface of said chip alongside of said n layer and providing for electrical connection from the silicon surface, through said p layer and beneath said n layer, to said subsurface junction; the concentration of p dopant in the region of said p layer which is centrally disposed beneath said n layer being substantially higher than the concentration of p dopant in the surface regions of said p layer which adjoin said n layer.
Claim 7
Dependent Claim
143 words
An IC chip presenting a buried Zener-diode junction comprising: a first layer of n dopant in the surface of the silicon layer of the chip; a second layer of p dopant having a first portion beneath said first layer and providing in its central regions a subsurface junction with said first layer; said second layer having a second portion extending out laterally beyond said first layer up to the silicon surface of said chip alongside of said n layer and providing for electrical connection from the silicon surface, through said p layer and beneath said n layer, to said subsurface junction; the concentration of p dopant in the region of said p layer which is centrally disposed beneath said n layer being substantially higher than the concentration of p dopant in the surface regions of said p layer which adjoin said n layer.
References Cited (Backward Citations)
US3378915A
Cited
US3881179A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-01-22 | 1982-07-24 | 1983-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-01-22 | 1986-07-24 | 1987-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-01-22 | 1990-07-24 | 1991-01-23 | $7700.00 | Window Closed / Lapsed |