Transponder decoder/encoder circuitry

Claim 1

In a transponder adapted to receive a coded interrogation signal having a plurality of input pulses, the improvement comprising: single clock means for producing a first series of clock pulses having a first predetermined frequency; a decoder means for decoding and validating said coded interrogation signal, said decoder means comprising validating circuitry and a decoder shift register connected to receive said input pulses and said first series of clock pulses, said decoder shift register being driven by said first series of clock pulses and operable with said validating circuitry to correlate said input pulses to determine the validity of said interrogation signal, said decoder means being operable to produce a validation signal in response to a determination that said interrogation signal is valid; means for providing a reply signal in response to said validation signal; means for deriving a second series of clock pulses from said first series of clock pulse said second series of clock pulses having the frequency different from the frequency of said first series of clock pulses; means for encoding said reply signal, said encoding means comprising an encoder shift register connected to receive said reply signal and said second series of clock pulses, said second series of clock pulses being operable to drive said encoder shift register to produce a coded reply signal in response to an interrogation signal that is valid; and synchronizing means for establishing a set time delay between production of said validation signal and production of said coded reply signal.

Claim 9

A method of validating and replying to an interrogation signal having first and second input pulses, said method comprising the steps of: producing a first series of clock pulses having a predetermined frequency; utilizing said first series of clock pulses to shift down the first input pulse of said interrogation signal from stage to stage; comparing said first pulse, after same has been shifted down a preselected number of stages, with the second pulse of said interrogation signal to determine whether there is time correlation therebetween and thus whether the interrogation signal is valid; producing a reply signal in response to the determination of a valid interrogation signal; deriving a second series of clock pulses from said first series of clock pulses having a different frequency than the first series; establishing a set time delay in response to the determination of a valid interrogation signal; and utilizing said second series of clock pulses after said set time delay to shift said reply signal in a manner to encode same, thereby providing a coded reply signal responsive to the interrogation signal.

Claim 10

A method of validating and replying to an interrogation signal having first and second input pulses, said method comprising the steps of: producing a first series of clock pulses having a predetermined frequency; utilizing said first series of clock pulses to shift down the first input pulse of said interrogation signal from stage to stage; comparing said first pulse, after same has been shifted down a preselected number of stages, with the second pulse of said interrogation signal to determine whether there is time correlation therebetween and thus whether the interrogation signal is valid; producing a reply signal in response to the determination of a valid interrogation signal; deriving a second series of clock pulses from said first series of clock pulses having a different frequency than the first series; establishing a set time delay in response to the determination of a valid interrogation signal; and utilizing said second series of clock pulses after said set time delay to shift said reply signal in a manner to encode same, thereby providing a coded reply signal responsive to the interrogation signal.