Methods of gray scale recording and archival memory target produced thereby

Claim 3

A method as set forth in claim 1, wherein step (c) includes the step of selecting the ions of said beam to be dopant ions imparting the first polarity-type to each auxiliary semiconductor region.

Claim 4

A method as set forth in claim 2, wherein step (d) comprises the steps of: maintaining the landing energy of the dopant ion beam at a substantially constant value; and varying the fluence of the beam to implant each auxiliary region with a substantially constant implantation depth and with one of a multiplicity of dopant concentrations each of said multiplicity of concentrations corresponding to an associated gray scale information value to be stored at an auxiliary region.

Claim 5

A method as set forth in claim 2, wherein step (c) comprises the steps of: maintaining the fluence of the dopant ion beam at a substantially constant value; and varying the landing energy of the beam to implant each auxiliary region with a substantially constant dopant concentration and with one of a multiplicity of depths into said fabricated layer, each of said multiplicity of depths corresponding to an associated value of gray scale information to be stored at an auxiliary region.

Claim 6

A method as set forth in claim 2, further comprising the step of annealing the target after dopant region implantation.

Claim 7

A method as set forth in claim 1, wherein step (c) includes the steps of: selecting the ions of said beam to be non-dopant ions; and damaging the semiconductor lattice of the fabricated layer by means of the beam of non-dopant ions to create each auxiliary region.

Claim 8

A method as set forth in claim 6, wherein step (d) comprises the steps of: maintaining the landing energy of the inert ions at a substantially constant value; and varying the fluence of the ions of the beam to create one of a multiplicity of amounts of damage at each potential data site in accordance with the value of an associated one of the multiplicity of gray scale data values to be stored thereat.

Claim 9

A method as set forth in claim 6, wherein step (d) comprises the steps of: maintaining the beam of inert ions at a constant fluence; and varying the landing energy of the ions creating the damage in accordance with the value of gray scale information to be stored thereat to vary the average damage depth into the fabricated layer to one of an associated multiplicity of depths.

Claim 10

A method as set forth in claim 1, further comprising the steps of: reverse biasing the junction between said layer and said substrate; scanning a focused beam of electrons to impinge sequentially upon each data site; and monitoring the current flow through said reverse-biased junction to derive an output from said target.

Claim 11

An archival memory target for substantially permanently gray scale information, comprising: a substrate of a semiconductor material of a first polarity-type; a continuous layer of said semiconductor material and of a remaining polarity-type, said layer being fabricated directly upon a major surface of said substrate to form a junction therebetween and having a top surface opposite said junction, said semiconductor layer having a two-dimensional array of possible data sites defined upon said top surface; and an auxiliary semiconductor region formed into said fabricated layer below said top surface at at least some of said possible data sites; a physical characteristic of each said auxiliary region being varied to one of a multiplicity of values to store in substantially non-erasable manner a corresponding one of a multiplicity of gray scale data values at each possible data site.

Claim 12

An archival memory target for substantially permanently gray scale information, comprising: a substrate of a semiconductor material of a first polarity-type; a continuous layer of said semiconductor material and of a remaining polarity-type, said layer being fabricated directly upon a major surface of said substrate to form a junction therebetween and having a top surface opposite said junction, said semiconductor layer having a two-dimensional array of possible data sites defined upon said top surface; and an auxiliary semiconductor region formed into said fabricated layer below said top surface at at least some of said possible data sites; a physical characteristic of each said auxiliary region being varied to one of a multiplicity of values to store in substantially non-erasable manner a corresponding one of a multiplicity of gray scale data values at each possible data site.

Claim 13

An archival memory target as set forth in claim 10, wherein said physical characteristic being varied is the dopant concentration.

Claim 14

An archival memory target as set forth in claim 11, wherein each auxiliary region is a doped semiconductor region of said first polarity-type.

Claim 15

An archival memory target as set forth in claim 12, wherein each said region has a substantially constant depth below said fabricated layer top surface.

Claim 16

An archival memory target as set forth in claim 10, wherein said physical characteristic being varied is the depth of each of said auxiliary regions below said fabricated layer top surface.

Claim 17

An archival memory target as set forth in claim 14, wherein each said auxiliary region is a doped semiconductor region of said first polarity-type.

Claim 18

An archival memory target as set forth in claim 15, wherein all of said auxiliary regions have substantially equal dopant concentrations.

Claim 19

An archival memory target as set forth in claim 14, wherein each of said auxiliary regions is a region of damage to the lattice of the semiconductor material of said fabricated layer.

Claim 20

An archival memory target as set forth in claim 10, wherein said physical characteristic being varied is the amount of damage to the lattice of the semiconductor material of said fabricated layer, said auxiliary regions having a substantially constant depth below said fabricated layer top surface.