Semiconductor switch

Claim 2

A semiconductor switch comprising: a pair of first and second PNPN switches each having a gate terminal and being connected in inverse-parallel relationship with each other between an AC power supply and a load, so that said PNPN switches are adapted for use where their cathode potentials float from ground potential to positive and negative potentials; a first and a second capacitive element, each of which is capable of blocking D.C. current flow in both directions therethrough; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, the gate terminal of said first PNPN switch being connected to said output terminal through said first capacitive element, and the gate terminal of said second PNPN switch being connected to said output terminal through said second capacitive element, to thereby drive said PNPN switches.

Claim 3

A semiconductor switch comprising: a pair of first and second PNPN switches each having at least three PN junctions and including four semiconductor regions comprised of an anode, an anode gate, a cathode gate and a cathode, said PNPN switches being connected in inverse-parallel relationship with each other between an AC power supply and a load, so that said PNPN switches are adapted for use where their cathode potentials float from ground potential to positive and negative potentials; two switch circuits each having an input and an output terminal connected across one of said PN junctions adjacent to one end region of said respective PNPN switches, and a control terminal supplied with a current derived from a current flowing through another one of said PN junctions adjacent to the other end region of said respective PNPN switches thereby to provide protection against the rate effect; a first and a second capacitive element; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, the cathode gate region of said first PNPN switch being connected to said output terminal through said first capacitive element, and the cathode gate region of said second PNPN switch being connected to said output terminal through said second capacitive element, to thereby drive said PNPN switches.

Claim 4

A semiconductor switch comprising: a pair of first and second PNPN switches each having at least three PN junctions and including four semiconductor regions comprised of an anode, an anode gate, a cathode gate and a cathode, said PNPN switches being connected in inverse-parallel relationship with each other between an AC power supply and a load, so that said PNPN switches are adapted for use where their cathode potentials float from ground potential to positive and negative potentials; two switch circuits each having an input and an output terminal connected across one of said PN junctions adjacent to one end region of said respective PNPN switches, and a control terminal supplied with a current derived from a current flowing through another one of said PN junctions adjacent to the other end region of said respective PNPN switches thereby to provide protection against the rate effect; a first and a second capacitive element; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, the cathode gate region of said first PNPN switch being connected to said output terminal through said first capacitive element, and the cathode gate region of said second PNPN switch being connected to said output terminal through said second capacitive element, to thereby drive said PNPN switches.

Claim 5

A semiconductor device as set forth in claim 2, wherein said capacitive element comprises a capacitor.

Claim 6

A semiconductor device as set forth in claim 2, wherein said capacitive element comprises the junction capacitance of a diode.

Claim 7

A semiconductor device as set forth in claim 2, wherein said capacitive element comprises two diodes connected in inverse-series relationship to provide a composite junction capacitance.

Claim 8

A semiconductor switch comprising: a pair of first and second PNPN switches each having at least three PN junctions and including four semiconductor regions comprised of an anode, an anode gate, a cathode gate and a cathode, said PNPN switches being connected in inverse-parallel relationship with each other between an AC power supply and a load, so that said PNPN switches are adapted for use where the cathode potentials thereof float from ground potential to positive and nagative potentials; two switch circuits each having an input and an output terminal connected respectively to said cathode gate and cathode regions, and a control terminal supplied with a current derived from a current flowing through one of said PN junctions adjacent to said anode region thereby to provide protection against the rate effect; a first and a second capacitive element; a first, a second, a third, and a fourth diode; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, said cathode gate region of said first PNPN switch being connected to said output terminal through a first series circuit of said first capacitive element and said first diode, said cathode gate region of said second PNPN switch being connected to said output terminal through a second series circuit of said second capacitive element and said second diode, said first and second diodes being so connected that their forward direction is a direction in which current flows into said cathode gate region, said third diode being connected between the cathode region of said first PNPN switches and an intermediate point of said first series circuit, said fourth diode being connected between the cathode region of said second PNPN swtich and an intermediate point of said second series circuit, said third and fourth diodes being so connected that their forward direction is toward said intermediate point.

Claim 9

A semiconductor switch comprising: a pair of first and second PNPN switches each having at least three PN junctions and including four semiconductor regions comprised of an anode, an anode gate, a cathode gate and a cathode, said PNPN switches being connected in inverse-parallel relationship with each other between an AC power supply and a load, so that said PNPN switches are adapted for use where the cathode potentials thereof float from ground potential to positive and nagative potentials; two switch circuits each having an input and an output terminal connected respectively to said cathode gate and cathode regions, and a control terminal supplied with a current derived from a current flowing through one of said PN junctions adjacent to said anode region thereby to provide protection against the rate effect; a first and a second capacitive element; a first, a second, a third, and a fourth diode; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, said cathode gate region of said first PNPN switch being connected to said output terminal through a first series circuit of said first capacitive element and said first diode, said cathode gate region of said second PNPN switch being connected to said output terminal through a second series circuit of said second capacitive element and said second diode, said first and second diodes being so connected that their forward direction is a direction in which current flows into said cathode gate region, said third diode being connected between the cathode region of said first PNPN switches and an intermediate point of said first series circuit, said fourth diode being connected between the cathode region of said second PNPN swtich and an intermediate point of said second series circuit, said third and fourth diodes being so connected that their forward direction is toward said intermediate point.

Claim 10

A semiconductor switch as set forth in claim 6, wherein said capacitive element comprises a capacitor.

Claim 11

A semiconductor switch as set forth in claim 6, wherein said capacitive element comprises a junction capacitance of a diode.

Claim 12

A semiconductor switch as set forth in claim 7, wherein said capacitive element comprises two diodes connected in inverse-series relationship to provide a composite junction capacitance.

Claim 13

A semiconductor switch comprising: a pair of first and second PNPN switches each having at least three PN junctions and including four semiconductor regions comprised of an anode, an anode gate, a cathode gate and a cathode, said PNPN switches being connected in inverse-parallel relationship with each other between an AC power supply and a load, so that said PNPN switches are adapted for use where the cathode potentials thereof float from groun potential to positive and negative potentials; two switch circuits each having an input and an output terminal connected respectively to said cathode gate and cathode regions, and a control terminal being supplied with current derived from current flowing through one of said PN junctions adjacent to said anode region to thereby provide protection against the rate effect; a first and a second capacitive element; a first, a second, a third, and a fourth diode; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, the anode gate region of said first PNPN switch being connected to said output terminal through a first series circuit of said first capacitive element and said first diode, the anode gate region of said second PNPN switch being connected to said output terminal through a second series circuit of said second capacitive element and said second diode, said first and second diodes being so connected that their forward direction is a direction in which a current is derived from said anode gate, said third diode being connected between the anode region of said first PNPN switch and an intermediate point of said first series circuit, said fourth diode being connected between the anode region of said second PNPN switch and an intermediate of said second series circuit, said third and fourth diodes being so connected that their forward direction is toward said intermediate point, thereby to drive said PNPN switches.

Claim 14

A semiconductor switch comprising: a pair of first and second PNPN switches each having at least three PN junctions and including four semiconductor regions comprised of an anode, an anode gate, a cathode gate and a cathode, said PNPN switches being connected in inverse-parallel relationship with each other between an AC power supply and a load, so that said PNPN switches are adapted for use where the cathode potentials thereof float from groun potential to positive and negative potentials; two switch circuits each having an input and an output terminal connected respectively to said cathode gate and cathode regions, and a control terminal being supplied with current derived from current flowing through one of said PN junctions adjacent to said anode region to thereby provide protection against the rate effect; a first and a second capacitive element; a first, a second, a third, and a fourth diode; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, the anode gate region of said first PNPN switch being connected to said output terminal through a first series circuit of said first capacitive element and said first diode, the anode gate region of said second PNPN switch being connected to said output terminal through a second series circuit of said second capacitive element and said second diode, said first and second diodes being so connected that their forward direction is a direction in which a current is derived from said anode gate, said third diode being connected between the anode region of said first PNPN switch and an intermediate point of said first series circuit, said fourth diode being connected between the anode region of said second PNPN switch and an intermediate of said second series circuit, said third and fourth diodes being so connected that their forward direction is toward said intermediate point, thereby to drive said PNPN switches.

Claim 15

A semiconductor switch comprising: a pair of first and second PNPN switches each having at least three PN junctions and including four semiconductor regions comprised of an anode, an anode gate, a cathode gate and a cathode, said PNPN switches being connected in inverse-parallel relationship between an AC power supply and a load, so that their cathode potentials float from ground potential to positive and negative potentials; two switch circuits each having an input and an output terminal connected respectively to said cathode gate and said cathode, and a control terminal supplied with current derived from current flowing through one of said PN junctions adjacent to said anode region to provide protection against the rate effect; a capacitive element; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, the anode gate regions of said first and second PNPN switches being formed in common and connected to said output terminal through said capacitive element, to thereby drive said PNPN switches.

Claim 16

A semiconductor switch comprising: a pair of first and second PNPN switches each having at least three PN junctions and including four semiconductor regions comprised of an anode, an anode gate, a cathode gate and a cathode, said PNPN switches being connected in inverse-parallel relationship between an AC power supply and a load, so that their cathode potentials float from ground potential to positive and negative potentials; two switch circuits each having an input and an output terminal connected respectively to said cathode gate and said cathode, and a control terminal supplied with current derived from current flowing through one of said PN junctions adjacent to said anode region to provide protection against the rate effect; a capacitive element; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, the anode gate regions of said first and second PNPN switches being formed in common and connected to said output terminal through said capacitive element, to thereby drive said PNPN switches.

Claim 17

A semiconductor switch comprising: a pair of first and second PNPN switches each having at least three PN junctions and including four semiconductor regions comprised of an anode, an anode gate, a cathode gate and a cathode, and a P-type collector region disposed on said anode gate region; said PNPN switches being connected in inverse-parallel relationship between an AC power supply and a load, so that their cathode potentials float from ground potential to positive and negative potentials; two switch circuits each having an input and an output terminal connected respectively to said cathode gate and cathode regions, and a control terminal supplied with a current derived from a current flowing through one of said PN junctions adjacent to said anode region to provide protection against the rate effect; a first and a second capacitive element; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, said cathode gate region of said first PNPN switch being connected to said output terminal through said first capacitive element, and said cathode gate region of said second PNPN switch being connected to said output terminal through said second capacitive element, to thereby drive said PNPN switches.

Claim 18

A semiconductor switch comprising: a pair of first and second PNPN switches each having at least three PN junctions and including four semiconductor regions comprised of an anode, an anode gate, a cathode gate and a cathode, and a P-type collector region disposed on said anode gate region; said PNPN switches being connected in inverse-parallel relationship between an AC power supply and a load, so that their cathode potentials float from ground potential to positive and negative potentials; two switch circuits each having an input and an output terminal connected respectively to said cathode gate and cathode regions, and a control terminal supplied with a current derived from a current flowing through one of said PN junctions adjacent to said anode region to provide protection against the rate effect; a first and a second capacitive element; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, said cathode gate region of said first PNPN switch being connected to said output terminal through said first capacitive element, and said cathode gate region of said second PNPN switch being connected to said output terminal through said second capacitive element, to thereby drive said PNPN switches.

Claim 19

A semiconductor switch comprising: a pair of first and second PNPN switches each having at least three PN junctions and including four semiconductor regions comprised of an anode, an anode gate, a cathode gate and a cathode, said PNPN switches being connected in inverse-parallel relationship between an AC power supply and a load, so that their cathode potentials float from ground potential to positive and negative potentials; two switch circuits each having input and output terminals connected respectively to said cathode gate and cathode regions, and a control terminal supplied with current derived from current flowing through one of said PN junctions adjacent to said anode region to provide protection against the rate effect; a first and a second capacitive element; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, the anode gate region of said first PNPN switch being connected to said output terminal through said first capacitive element, and the anode gate region of said second PNPN switches being connected to said output terminal through said second capacitive element, to thereby drive said PNPN switches.

Claim 20

A semiconductor switch comprising: a pair of first and second PNPN switches each having at least three PN junctions and including four semiconductor regions comprised of an anode, an anode gate, a cathode gate and a cathode, said PNPN switches being connected in inverse-parallel relationship between an AC power supply and a load, so that their cathode potentials float from ground potential to positive and negative potentials; two switch circuits each having input and output terminals connected respectively to said cathode gate and cathode regions, and a control terminal supplied with current derived from current flowing through one of said PN junctions adjacent to said anode region to provide protection against the rate effect; a first and a second capacitive element; and a control circuit having an output terminal for generating a voltage pulse in a repetitive manner, the anode gate region of said first PNPN switch being connected to said output terminal through said first capacitive element, and the anode gate region of said second PNPN switches being connected to said output terminal through said second capacitive element, to thereby drive said PNPN switches.