Patent JPS563427A successfully refreshed from Google Patents.
US4129830A
Expired / Lapsed
US
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Counting process for time-to-digital converting circuits
Assignee: Japan Atomic Energy Agency
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Filing: 1977-05-25
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Granted: 1978-12-12
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Expires: 1997-05-25
Abstract
Abstract A phase that a scaler is operated by gated clock-pulses is made different from another phase that the scaler is operated by the gated clock-pulses at every conversion cycle. The phases in which the operation of the scaler interferes with the clock-pulses and gate circuits are varied at random so that the interfering action is dispersed and an averaging action is obtained.
Inventors
- 👤 Setsuro Kinbara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:31
CPC Classifications
G; G04; G04F; G04F10/00; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/033; H; H03; H03M; H03M1/00; H03M1/12; H03M1/124; H03M1/1245; H03M1/1255
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
264 words
In a time-to-digital circuit, an apparatus for counting a pulse train obtained by gating clock-pulses by means of time signals to obtain digital values comprising: a synchronizing circuit connected to a terminal of time signals for synchronizing the phases of said clock-pulses with the phases of said time signals, a shift scaling circuit having a plurality of stages, including a binary coded unit, connected to the synchronizing circuit for shifting the time signals applied to the shift scaling circuit in accordance with the period of the clock pulses to obtain outputs from every stage of the shift scaling circuit, a control scaling circuit having the same number of ordered outputs as the number of outputs of said shift scaling circuit and connected to a terminal of reset signals, a plurality of selecting gates, each selecting gate having the same number of stages as those in the shift scaling circuit and connected to the shift scaling circuit and the control scaling circuit for applying one of the outputs obtained from the stages of the shift scaling circuit to the selecting gate to select a time signal by an ordered output signal of the control scaling circuit, said ordered output signal being provided by the control scaling circuit through being advanced every converting cycle, and And gate means connected to the selecting circuit for directly controlling the clock-pulses and for obtaining a pulse train with a number proportional to the number of the period of the time signals by gating the clock-pulses by the AND gate by means of the synchronized, shifted and selected time signals.
Claim 2
Dependent Claim
264 words
In a time-to-digital circuit, an apparatus for counting a pulse train obtained by gating clock-pulses by means of time signals to obtain digital values comprising: a synchronizing circuit connected to a terminal of time signals for synchronizing the phases of said clock-pulses with the phases of said time signals, a shift scaling circuit having a plurality of stages, including a binary coded unit, connected to the synchronizing circuit for shifting the time signals applied to the shift scaling circuit in accordance with the period of the clock pulses to obtain outputs from every stage of the shift scaling circuit, a control scaling circuit having the same number of ordered outputs as the number of outputs of said shift scaling circuit and connected to a terminal of reset signals, a plurality of selecting gates, each selecting gate having the same number of stages as those in the shift scaling circuit and connected to the shift scaling circuit and the control scaling circuit for applying one of the outputs obtained from the stages of the shift scaling circuit to the selecting gate to select a time signal by an ordered output signal of the control scaling circuit, said ordered output signal being provided by the control scaling circuit through being advanced every converting cycle, and And gate means connected to the selecting circuit for directly controlling the clock-pulses and for obtaining a pulse train with a number proportional to the number of the period of the time signals by gating the clock-pulses by the AND gate by means of the synchronized, shifted and selected time signals.
Claim 3
Dependent Claim
199 words
In a time-to-digital circuit, an apparatus for counting a pulse train obtained by gating clock pulses by means of time signals to obtain digital values comprising: a continuously oscillating clock oscillator, an AND gate connected to the clock oscillator for gating clock pulses from the clock oscillator by means of time signals to obtain a pulse train, a shift scaling circuit for counting the pulse train obtained by the gating process in the AND gate, and a delay control circuit connected between the AND gate and the shift scaling circuit, said delay control circuit including a plurality of selecting gates, a plurality of delay elements each connected to a respective selecting gate and having a difference in time delay of one period of the clock pulses, a plurality of OR gates each connected to a respective delay element, and a delay selecting circuit connected to the selecting gates, whereby the delay selecting circuit applies the pulse train that is gated by the AND gate to a respective one of said delay elements through a respective one of the selecting gates at each measuring cycle to select and control the respective one of the delay elements in an arbitrary order.
Claim 4
Dependent Claim
199 words
In a time-to-digital circuit, an apparatus for counting a pulse train obtained by gating clock pulses by means of time signals to obtain digital values comprising: a continuously oscillating clock oscillator, an AND gate connected to the clock oscillator for gating clock pulses from the clock oscillator by means of time signals to obtain a pulse train, a shift scaling circuit for counting the pulse train obtained by the gating process in the AND gate, and a delay control circuit connected between the AND gate and the shift scaling circuit, said delay control circuit including a plurality of selecting gates, a plurality of delay elements each connected to a respective selecting gate and having a difference in time delay of one period of the clock pulses, a plurality of OR gates each connected to a respective delay element, and a delay selecting circuit connected to the selecting gates, whereby the delay selecting circuit applies the pulse train that is gated by the AND gate to a respective one of said delay elements through a respective one of the selecting gates at each measuring cycle to select and control the respective one of the delay elements in an arbitrary order.
References Cited (Backward Citations)
US3524131A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-12-11 | 1982-06-12 | 1982-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-12-11 | 1986-06-12 | 1986-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-12-11 | 1990-06-12 | 1990-12-12 | $7700.00 | Window Closed / Lapsed |