Digitally controlled power system

Claim 2

A digitally controlled power system controlled during timed clock cycles comprising: at least one power supply responsive to a pair of control pulses each having a pulse width providing a controlled output voltage, means for sensing a difference between a reference voltage and said output voltage whereby said means provides an error signal representative of said difference, digital control processor means connected to receive and process said error signal and to provide said pair of control pulses during said clock cycles, and control memory means connected to said processor means to provide a program of instructions to said processor means such that said processor means provides a programmed change in the width of said control pulses whereby said power supply provides a change in said output voltage.

Claim 3

A system as in claim 1 wherein said means for sensing includes analog to digital converter means for converting said error signal to a binary signal representative of a binary number.

Claim 4

A system as in claim 2 wherein said program of instructions includes a program for proportional control of said control pulses.

Claim 5

A system as in claim 2 wherein said program of instructions includes a program for derivative control of said control pulses.

Claim 6

A system as in claim 2 wherein said program of instructions includes a program for integral control of said control pulses.

Claim 7

A system as in claim 2 wherein said program of instructions includes a time of day clock program for turning on or off said power supply.

Claim 8

A system as in claim 2 wherein said processor means includes program counter means for generating the address of an instruction to be fetched from said control memory means, instruction register means for loading said instruction from said control memory means, and decoder means for decoding said instruction.

Claim 9

A system as in claim 2 wherein said processor means includes pulse width register means for storing a binary number representative of the width of said control pulses, pulse width counter means incrementable once each clock cycle from an initial count and reset to said initial count when said counter means reaches a predetermined count, and comparator means to compare said number stored in said pulse width register means with the count in said pulse width counter means.

Claim 10

A system as in claim 8 wherein said processor means include buffer driver means connected to said comparator means for transmitting said control pulses to said power supply whereby said driver means initiates said control pulses at said initial count and terminates said control pulses when said number equals the count in said pulse width counter means.

Claim 11

A system as in claim 8 wherein said processor means includes register file means having an error voltage register for storing said error signal during one clock cycle, a working register for storing another error signal from another clock cycle, and a pulse register for storing a control pulse to be loaded into said pulse width register means.

Claim 12

A system as in claim 10 wherein said register file means includes a save register for saving the address in said control memory means of the program to be initiated when the power supply associated with said register is to be serviced.

Claim 13

A system as in claim 10 wherein said processor means includes arithmetic logic unit means for computing the difference between said error signal and said another error signal thereby forming a derivative signal and for computing the difference between said control pulse and said derivative signal thereby forming a regulation pulse.

Claim 14

A system as in claim 12 wherein said arithmetic logic unit means includes means for computing another difference between said regulation pulse and the sum of said derivative and said another error signal thereby forming a recovery pulse when said another difference exceeds said predetermined count.

Claim 15

A system as in claim 13 wherein said control pulses include a proportional pulse for one clock cycle and a derivative pulse for another clock cycle.

Claim 16

A digitally controlled power system controlled during timed clock cycles comprising: a plurality of power supplies each responsive to a pair of control pulses each having a pulse width providing a controlled output voltage, means for sensing a difference between a reference voltage and said output voltage for each power supply, thereby forming an error signal for each power supply, digital control processor means connected to receive and process said error signal representative of said difference for each power supply and to provide said pair of control pulses during said clock cycles, multiplexer means for sequentially connecting said processor means to each of said power supplies and to said means for sensing, and control memory means connected to said processor means to provide a program of instructions to said processor means whereby said processor means provides a programmed change in the width of said control pulses for each power supply such that each power supply provides a change in said output voltage.

Claim 17

A digitally controlled power system controlled during timed clock cycles comprising: a plurality of power supplies each responsive to a pair of control pulses each having a pulse width providing a controlled output voltage, means for sensing a difference between a reference voltage and said output voltage for each power supply, thereby forming an error signal for each power supply, digital control processor means connected to receive and process said error signal representative of said difference for each power supply and to provide said pair of control pulses during said clock cycles, multiplexer means for sequentially connecting said processor means to each of said power supplies and to said means for sensing, and control memory means connected to said processor means to provide a program of instructions to said processor means whereby said processor means provides a programmed change in the width of said control pulses for each power supply such that each power supply provides a change in said output voltage.

Claim 18

A system as in claim 15 wherein said multiplexer means includes analog switch means.

Claim 19

A system as in claim 15 wherein said processor means includes pulse width register means associated with each power supply for storing said control pulses to be output, pulse width counter means incrementable once each clock cycle from an initial count and reset when said pulse width counter means reaches a predetermined count and, comparator means associated with each power supply to compare the control pulse stored in said pulse width register means with the count in said pulse width counter means.

Claim 20

A system as in claim 17 wherein said processor means includes a register file bank for each power supply wherein each of the register files includes an error voltage register for storing said error signal during one clock cycle, a working register for storing another error signal from a previous clock cycle, a pulse register for storing the control pulses to be output, and a save register for saving the address in said control memory means of the program to be initiated when the power supply associated with said bank is to be serviced.

Claim 21

A system as in claim 18 including arithmetic logic unit means for computing the difference for each of said power supplies between said error signal and said another error signal thereby forming a derivative signal and for comparing the difference between a control pulse and said derivative signal thereby forming a regulation pulse, and for computing the difference between said regulation pulse and the sum of said derivative and said another error signal thereby forming a recovery pulse when said recovery pulse exceeds said predetermined count.

Claim 22

A system as in claim 19 further including control counter means incrementable once each time said pulse width counter means reaches said predetermined count whereby said control counter means sequentially activates each of said power supplies, comparator means, and pulse width register means.

Claim 23

A system as in claim 16 wherein said analog switch means incudes means for independently sequencing the turning on or off of said plurality of power supplies in said power system.

Claim 24

A system as in claim 15 wherein said power supplies are adjustable from a remote source.

Claim 25

A system as in claim 16 wherein said analog switch means includes a decimal display for visual monitoring of said error signal.

Claim 26

A digitally controlled power system controlled during timed clock cycles comprising: at least one power supply responsive to one or more control pulses each having a pulse width providing a controlled output voltage, means for sensing a difference between a reference voltage and said output voltage whereby said means provides an error signal representative of said difference, digital control processor means connected to receive and process said error signal and to provide said control pulses during said clock cycles, and control memory means connected to said processor means to provide a program of instructions to said processor means such that said processor means provides a programmed change in the width of said control pulses whereby said power supply provides a change in said output voltage.

Claim 27

A digitally controlled power system controlled during timed clock cycles comprising: at least one power supply responsive to one or more control pulses each having a pulse width providing a controlled output voltage, means for sensing a difference between a reference voltage and said output voltage whereby said means provides an error signal representative of said difference, digital control processor means connected to receive and process said error signal and to provide said control pulses during said clock cycles, and control memory means connected to said processor means to provide a program of instructions to said processor means such that said processor means provides a programmed change in the width of said control pulses whereby said power supply provides a change in said output voltage.

Claim 28

A system as in claim 24 wherein said processor means includes means for differentiating the leading edge of said control pulses thereby forming a start pulse.

Claim 29

A system as in claim 24 wherein said processor means includes means for differentiating the trailing edge of said control pulses thereby forming a stop pulse.

Claim 30

A digitally controlled power system controlled during timed system cycles and including at least one power supply responsive to a pair of control pulses each having a pulse width providing a controlled output voltage, the improvement comprising the steps of: storing under control of programmed instructions a first error signal comprising the difference between a reference voltage and an output voltage in one clock cycle and storing a second error signal in another clock cycle, comparing under control of said instructions said first signal with said second signal thereby forming a derivative signal, comparing under control of said instructions said control pulses and said derivative signal thereby forming new control pulses, each with a new pulse width, transmitting under control of said instructions said new control pulses during said system cycles to said power supply thereby providing a programmed change in said output voltage in response to said new control pulses.

Claim 31

A digitally controlled power system controlled during timed system cycles and including at least one power supply responsive to a pair of control pulses each having a pulse width providing a controlled output voltage, the improvement comprising the steps of: storing under control of programmed instructions a first error signal comprising the difference between a reference voltage and an output voltage in one clock cycle and storing a second error signal in another clock cycle, comparing under control of said instructions said first signal with said second signal thereby forming a derivative signal, comparing under control of said instructions said control pulses and said derivative signal thereby forming new control pulses, each with a new pulse width, transmitting under control of said instructions said new control pulses during said system cycles to said power supply thereby providing a programmed change in said output voltage in response to said new control pulses.