US4128743A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for blocking a bidirectional amplifier against receiving outgoing signals
Assignee: Wincor Nixdorf International GmbH
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Filing: 1976-09-30
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Granted: 1978-12-05
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Expires: 1996-09-30
Abstract
Abstract A circuit for the reciprocal transmission of signals through transmitting channels. The circuit has amplifiers therein for amplifying the signals being transmitted in opposite directions along the line. A pair of electronic hybrid circuits are provided so that the signals which are emitted by one amplifier and which must be transmitted in one direction do not overdrive the input of a further amplifier which is provided for amplification of signals to be transmitted in the other direction. A circuit is provided in each of the electronic hybrid circuits for the continuous production of a reference signal which is fed to a comparator circuit connected to the input of the amplifier so that the signals arriving at the amplifier can be compared with the outgoing signals that are being transmitted in the opposite direction. The reference voltage is controlled with respect to its magnitude and phase so that it corresponds to the voltage produced by the outgoing signals and any difference existing between the reference voltage and the outgoing signals will cause the comparator circuit to produce a signal to effectively prevent the outgoing signals from reaching the input to the amplifier.
Inventors
- 👤 Josef Huellwegen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:25
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/20; H04L25/22
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
418 words
A bidirectional amplifier circuit arrangement for use in a bidirectional transmission line to prevent first signals travelling in a first direction from interfering with second signals travelling in a second direction, comprising: means defining a pair of separate circuits through said bidirectional amplifier circuit; a pair of electronic hybrid circuits positioned at the juncture between the ends of said pair of separate circuits and the mutually adjacent ends of said transmission line, each of said electronic hybrid circuits having a first input terminal connected to one of said ends of said transmission line, a second input terminal connected to one of said ends of one of said separate circuits and an output terminal connected to one of said ends of the other of said separate circuits, said electronic hybrid circuits further including: (a) reference voltage generating means having an input connected in circuit with said first input terminal for continuously producing a first voltage signal at the output thereof in response to the impedance characteristic of said one of said transmission lines connected to said first input terminal, said reference voltage generator means including a variable resistor network for reproducing the capacitive and the resistive characteristics of said one of said transmission lines; (b) signal producing means connected in circuit with said first input terminal and said input to said reference voltage generating means for producing a second voltage signal in response to said second signal from the other of said transmission lines connected in circuit with said second input terminal; (c) means operatively connected to said variable resistor network of said reference voltage generating means for superposing a control of the magnitude and phase of said first voltage signal thereby producing a third voltage signal corresponding to the magnitude and phase of said second signal; (d) comparator circuit means operatively connected to said output from said reference voltage generating means and said first input terminal for comparing said second and third voltage signals thereat and effecting the production of a fourth voltage signal in response thereto; and (e) means operatively connected to said comparator circuit means and being responsive to said fourth voltage signal for controlling said superposing means for effecting a cancelling of said second signal thereby preventing it from reaching said output terminal while simultaneously transmitting said second signal to said one of said ends of said transmission line and remaining ready to receive said first signals from said one of said ends of said transmission lines and passing them through to said output terminal.
Claim 2
Dependent Claim
418 words
A bidirectional amplifier circuit arrangement for use in a bidirectional transmission line to prevent first signals travelling in a first direction from interfering with second signals travelling in a second direction, comprising: means defining a pair of separate circuits through said bidirectional amplifier circuit; a pair of electronic hybrid circuits positioned at the juncture between the ends of said pair of separate circuits and the mutually adjacent ends of said transmission line, each of said electronic hybrid circuits having a first input terminal connected to one of said ends of said transmission line, a second input terminal connected to one of said ends of one of said separate circuits and an output terminal connected to one of said ends of the other of said separate circuits, said electronic hybrid circuits further including: (a) reference voltage generating means having an input connected in circuit with said first input terminal for continuously producing a first voltage signal at the output thereof in response to the impedance characteristic of said one of said transmission lines connected to said first input terminal, said reference voltage generator means including a variable resistor network for reproducing the capacitive and the resistive characteristics of said one of said transmission lines; (b) signal producing means connected in circuit with said first input terminal and said input to said reference voltage generating means for producing a second voltage signal in response to said second signal from the other of said transmission lines connected in circuit with said second input terminal; (c) means operatively connected to said variable resistor network of said reference voltage generating means for superposing a control of the magnitude and phase of said first voltage signal thereby producing a third voltage signal corresponding to the magnitude and phase of said second signal; (d) comparator circuit means operatively connected to said output from said reference voltage generating means and said first input terminal for comparing said second and third voltage signals thereat and effecting the production of a fourth voltage signal in response thereto; and (e) means operatively connected to said comparator circuit means and being responsive to said fourth voltage signal for controlling said superposing means for effecting a cancelling of said second signal thereby preventing it from reaching said output terminal while simultaneously transmitting said second signal to said one of said ends of said transmission line and remaining ready to receive said first signals from said one of said ends of said transmission lines and passing them through to said output terminal.
Claim 3
Dependent Claim
56 words
The circuit arrangement according to claim 1, wherein the comparator circuit means is arranged before said output and comprises a MOS field effect transistor having a gate electrode, a source electrode and a drain electrode, said gate electrode being controlled by said third voltage signal, and said source electrode having said second voltage signal applied thereto.
Claim 4
Dependent Claim
197 words
The circuit arrangement according to claim 2, in particular for the transmission of digital signals, wherein said variable resistor network includes variable resistors and wherein for adjusting the variable resistors of said variable resistor network, said superposing means is provided which includes first and second control loops which each contain an integral control circuit, said first control loop being operatively connected to one of said variable resistors and to said second input terminal through a first signal duration control device operable for a first predetermined time (τ1) and said second control loop being operatively connected to the other of said variable resistors through a second signal duration control device operable for a second predetermined time (τ2), wherein said first control loop is switched active for said first predetermined time (τ1) prior to the rising edge of each one of said second signals applied to said second input terminal and for a second predetermined time (τ2) after the rising edge of each one of said second signals and wherein said second control loop is switched active for the remaining time of said second signals delayed by the sum of said first and second predetermined times (τ1 + τ2).
Claim 5
Dependent Claim
24 words
The circuit arrangement according to claim 3, wherein said two variable resistors are photoresistors, said photoresistors being opto-electronically coupled to said integral control circuits.
Claim 6
Dependent Claim
80 words
The circuit arrangement according to claim 4, wherein a first one of said photoresistors controls a capacitive shunt to said second voltage signal which is applied to said first input terminal and a second one of said photoresistors controls an ohmic shunt to said second voltage signals and which is connected to said first input terminal at a circuit point (C) to which is fed the input voltage produced by the arriving signals on said one of said transmission lines.
Claim 7
Dependent Claim
21 words
The circuit arrangement according to claim 5, wherein said integral control circuits are coupled to said photoresistors through light emitting diodes.
Claim 8
Dependent Claim
72 words
The circuit arrangement according to claim 3, wherein control signals for switching active said two control loops are produced by said second signals to effectively alter the length of said second voltage signal to correspond with the sum of said first and second predetermined times (τ1 + τ2), and wherein said second voltage signal is produced following a delay of said first predetermined time (τ1) from the occurrence of said second signals.
Claim 9
Dependent Claim
68 words
The circuit arrangement according to claim 2, wherein said comparator circuit means further includes a high-frequency resonant circuit comprising an inductance and capacitance and a galvanic coupling device operatively connecting said high-frequency resonant circuit between said drain and source electrodes of said MOS field effect transistor, said MOS field effect transistor functioning as a modulation element for said high-frequency resonant circuit which is part of a decoupling transmitter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-12-04 | 1982-06-05 | 1982-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-12-04 | 1986-06-05 | 1986-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-12-04 | 1990-06-05 | 1990-12-05 | $7700.00 | Window Closed / Lapsed |