Balanced capacitance charge transfer device

Claim 2

A semiconductor electrical charge transfer device comprising: a first plurality of spaced conductive charge transfer electrodes insulatingly disposed on a major surface of a semiconductor substrate and defining quiescent and signal charge storage locations along a signal transfer path, said first plurality comprising a first set of conductive areas coupled to a first conductor and having an associated first capacitance developed in response to charge underlying said first set of conductive areas, and a second set of conductive areas coupled to a second conductor and having an associated second capacitance developed in response to charge underlying said second set of conductive areas; a second plurality of a predetermined number of spaced conductive electrodes insulatingly disposed on said major surface of said semiconductor substrate and defining quiescent charge storage locations of an auxiliary path adjacent to said signal transfer path, each electrode of said second plurality having an associated capacitance developed in response to charge underlying each of said electrodes; means for conductively coupling said second plurality of electrodes to one of said first and second conductors; and wherein said number of electrodes of said auxiliary path is chosen so that quiescent capacitances respectively associated with said first and second conductors exhibit a predetermined ratio different from the ratio of said first capacitance to said second capacitance.

Claim 3

A device according to claim 1, wherein: said charge transfer device comprises a charge coupled device.

Claim 4

A device according to claim 1, wherein: said predetermined number of electrodes of said second plurality is chosen so that said capacitances respectively associated with said first and second conductors and exhibiting said predetermined ratio are substantially equal.

Claim 5

A device according to claim 1, wherein: said charge underlying said electrodes of said second plurality is dynamically adjustable in magnitude.

Claim 6

An arrangement according to claim 1, wherein: said signal transfer path and said auxiliary path are of substantially equal width.

Claim 7

A semiconductor electrical charge transfer device comprising: a first plurality of spaced conductive charge transfer electrodes insulatingly disposed on a major surface of a semiconductor substrate and defining quiescent and signal charge storage locations along a signal transfer path, said first plurality comprising a first set of conductive areas coupled to a first conductor and having an associated first capacitance developed in response to charge underlying said first set of conductive areas, and a second set of conductive areas coupled to a second conductor and having an associated second capacitance developed in response to charge underlying said second set of conductive areas; a second plurality of spaced intermediate charge transfer electrodes insulatingly disposed on said major surface of said semiconductor substrate and defining charge storage locations along said signal transfer path, said intermediate electrodes being disposed individually between said electrodes of said first plurality; a third plurality of a predetermined number of spaced conductive electrodes insulatingly disposed on said major surface of said semiconductor substrate and defining quiescent charge storage locations of an auxiliary path adjacent to said signal transfer path, each electrode of said third plurality having an associated capacitance developed in response to charge underlying each of said electrodes; means for conductively coupling said third plurality of electrodes of one of said first and second conductors; and wherein said number of electrodes of said auxiliary path is chosen so that quiescent capacitances respectively associated with said first and second conductors exhibit a balanced relationship different from the relationship of said first capacitance to said second capacitance.

Claim 8

A semiconductor electrical charge transfer device comprising: a first plurality of spaced conductive charge transfer electrodes insulatingly disposed on a major surface of a semiconductor substrate and defining quiescent and signal charge storage locations along a signal transfer path, said first plurality comprising a first set of conductive areas coupled to a first conductor and having an associated first capacitance developed in response to charge underlying said first set of conductive areas, and a second set of conductive areas coupled to a second conductor and having an associated second capacitance developed in response to charge underlying said second set of conductive areas; a second plurality of spaced intermediate charge transfer electrodes insulatingly disposed on said major surface of said semiconductor substrate and defining charge storage locations along said signal transfer path, said intermediate electrodes being disposed individually between said electrodes of said first plurality; a third plurality of a predetermined number of spaced conductive electrodes insulatingly disposed on said major surface of said semiconductor substrate and defining quiescent charge storage locations of an auxiliary path adjacent to said signal transfer path, each electrode of said third plurality having an associated capacitance developed in response to charge underlying each of said electrodes; means for conductively coupling said third plurality of electrodes of one of said first and second conductors; and wherein said number of electrodes of said auxiliary path is chosen so that quiescent capacitances respectively associated with said first and second conductors exhibit a balanced relationship different from the relationship of said first capacitance to said second capacitance.

Claim 9

A signal processing arrangement formed of semiconductor electrical charge transfer elements, comprising: a first plurality of serially spaced conductive charge transfer electrodes insulatingly disposed on a major surface of a semiconductor substrate and defining quiescent and signal charge storage locations along a signal transfer path, said first plurality comprising a first set of conductive areas coupled to a first conductor and having an associated first capacitance developed in response to charge underlying said first set of conductive areas, and a second set of conductive areas coupled to a second conductor and having an associated second capacitance developed in response to charge underlying said second set of conductive areas; a source of input signals coupled to said signal transfer path; a source of first clock signals coupled to said first and second sets of conductive areas; a second plurality of serially spaced, intermediate charge transfer electrodes insulatingly disposed on said major surface of said semiconductor substrate and defining charge storage locations along said signal transfer path, said intermediate electrodes being disposed individually between said electrodes of said first plurality; a source of second clock signals of a different phase than said first clock signals coupled to said intermediate electrodes; differential signal combining means having first and second inputs coupled to said first and second conductors, respectively; a third plurality of a predetermined number of spaced conductive electrodes insulatingly disposed on said major surface of said semiconductor substrate and defining quiescent charge storage locations of an auxiliary path adjacent to said signal transfer path, each electrode of said third plurality having an associated capacitance developed in response to charge underlying each of said electrodes; a fourth plurality of intermediate charge transfer electrodes insulatingly disposed on said major surface of said semiconductor substrate and disposed individually between said electrodes of said third plurality, and coupled to said source of second clock signals; means for conductively coupling said third plurality of electrodes to one of said first and second conductors; and wherein said number of electrodes of said auxiliary path is chosen so that quiescent capacitances respectively associated with said first and second conductors exhibit a balanced relationship different from the relationship of said first capacitance to said second capacitance.

Claim 10

A signal processing arrangement formed of semiconductor electrical charge transfer elements, comprising: a first plurality of serially spaced conductive charge transfer electrodes insulatingly disposed on a major surface of a semiconductor substrate and defining quiescent and signal charge storage locations along a signal transfer path, said first plurality comprising a first set of conductive areas coupled to a first conductor and having an associated first capacitance developed in response to charge underlying said first set of conductive areas, and a second set of conductive areas coupled to a second conductor and having an associated second capacitance developed in response to charge underlying said second set of conductive areas; a source of input signals coupled to said signal transfer path; a source of first clock signals coupled to said first and second sets of conductive areas; a second plurality of serially spaced, intermediate charge transfer electrodes insulatingly disposed on said major surface of said semiconductor substrate and defining charge storage locations along said signal transfer path, said intermediate electrodes being disposed individually between said electrodes of said first plurality; a source of second clock signals of a different phase than said first clock signals coupled to said intermediate electrodes; differential signal combining means having first and second inputs coupled to said first and second conductors, respectively; a third plurality of a predetermined number of spaced conductive electrodes insulatingly disposed on said major surface of said semiconductor substrate and defining quiescent charge storage locations of an auxiliary path adjacent to said signal transfer path, each electrode of said third plurality having an associated capacitance developed in response to charge underlying each of said electrodes; a fourth plurality of intermediate charge transfer electrodes insulatingly disposed on said major surface of said semiconductor substrate and disposed individually between said electrodes of said third plurality, and coupled to said source of second clock signals; means for conductively coupling said third plurality of electrodes to one of said first and second conductors; and wherein said number of electrodes of said auxiliary path is chosen so that quiescent capacitances respectively associated with said first and second conductors exhibit a balanced relationship different from the relationship of said first capacitance to said second capacitance.

Claim 11

An arrangement according to claim 7, wherein: said clock signals from said first and second sources are of mutually opposite phase.

Claim 12

An arrangement according to claim 8, wherein: said clock signals from said first source are capacitively coupled to said first and second conductive areas.

Claim 13

An arrangement according to claim 8, wherein: said first and second sets of conductive areas of said first plurality of electrodes are arranged as signal weighting electrodes of a transversal filter.

Claim 14

An arrangement according to claim 8, wherein: electrodes of said first plurality are defined by first and second electrode portions having predetermined first and second surface areas, a sum of said first electrode portions comprising said first set of conductive areas, a sum of said second electrode portions comprising said second set of conductive areas, and the ratio between said first and second areas of each electrode portion being determinative of a selected signal weighting factor.

Claim 15

An arrangement according to claim 11, wherein: said arrangement comprises a transversal filter with said first and second sets of conductive areas being of relatively unequal surface area.