Electronic phase detector circuit

Claim 1

A phase detector circuit comprising: (a) sawtooth signal generator means including: (i) a resistive means, (ii) a capacitive means serially coupled to said resistive means, and (iii) a switching means coupled in parallel with said capacitive means, said switching means having an input coupled to receive a reference clock signal with said switch being responsive to the voltage levels of said reference clock signal for selectively providing high and low impedence paths in parallel with said capacitive means to generate a sawtooth-shaped signal of the same period as said reference clock signal; and (b) sample-and-hold circuit means comprised of: (i) a first MOS transistor having source, drain and gate electrodes, the source electrode being coupled to said sawtooth generator means for receiving said sawtooth-shaped signal, and the gate electrode being coupled to receive a digital sampling clock signal of selectively controllable clock rate; (ii) an MOS load transistor, (iii) an MOS source transistor serially coupled to said load transistor, said source transistor having a gate electrode coupled to the drain electrode of said first MOS transistor for receiving samples of said sawtooth-shaped signal and having a Miller capacitance for holding the most current sample of said sawtooth-shaped signal, and (iv) output means coupled to said source transistor for generating a phase detection signal of a magnitude proportional to the magnitude of the samples held by said Miller capacitance.