Delayed kinescope blanking pulse generator

Claim 2

A delayed transition blanking pulse generator for a television kinescope deflection apparatus synchronized from a source of synchronizing signals initiating but preceding a blanking pulse transition, comprising: first current source means of a first polarity; capacitance means coupled to said first current source means for accepting first charging current therefrom to form an integrated signal; controllable second current source means coupled to said capacitance means for producing a second charging current therein of an opposite polarity and greater amplitude than that of said first current source; first coupling means for coupling a control electrode of said controllable second current source to the source of synchronizing signals; voltage-sensitive switch means coupled to said capacitance means for generating a blanking signal pulse component of a first polarity at an output terminal when said integrated signal exceeds a predetermined value; and current-sensitive switch means coupled to said second current source and to said output terminal and responsive to generation of said second charging current to produce a blanking signal pulse component of said first polarity.

Claim 3

A delayed transistor blanking pulse generator according to claim 1 wherein said current-sensitive switch means is coupled to said capacitance means and inhibited by particular values of said integrated signal.

Claim 4

A delayed transistor blanking pulse generator according to claim 1 wherein said first current source comprises resistance means coupled in series with constant-voltage biasing means and the series combination of said resistance means and said biasing means is coupled across a source of constant operating potential.

Claim 5

A delayed transistor blanking pulse generator according to claim 3 wherein said blanking pulse generator is substantially comprised within an integrated circuit and said resistance means is extrinsic to said integrated circuit.

Claim 6

A delayed transistor delayed blanking generator according to claim 3 wherein said biasing means comprises forward-biased diode means and further comprises output transistor means biased by said forward-biased diode means and having a collector coupled to the output of said first current source means for producing a current of said first polarity.

Claim 7

A delayed transistor blanking pulse generator according to claim 5 wherein said capacitance means has a first electrode coupled to a source of reference potential and a second electrode coupled to said collector of said output transistor means at a point for forming a ramp voltage.

Claim 8

A delayed transistor blanking pulse generator according to claim 1 wherein said controllable second current source comprises second current source means; current mirror means coupled to an output of said second current source means for producing said second charging current; and switch means coupled to said second current source means and having a control electrode forming said control electrode of said controllable second current source means.

Claim 9

A delayed transistor blanking pulse generator according to claim 1 wherein said current-sensitive switch means comprises a current-sensitive transistor having an emitter coupled to an output terminal of said controllable second current source means, a base coupled to said capacitance means and a collector coupled to said output terminal of said blanking pulse generator.

Claim 10

A delayed transistor blanking pulse generator according to claim 1 wherein said voltage-sensitive switch means comprises a voltage-sensitive switch transistor having a base electrode coupled to said capacitance means at a point and having a collector electrode coupled to the output terminal of said blanking pulse generator.

Claim 11

A delayed transistor blanking pulse generator according to claim 9 wherein said collector electrode of said voltage-sensitive switch transistor is coupled to a point of reference potential by collector load means.

Claim 12

A delayed transistor blanking pulse generator according to claim 9 wherein the emitter collector of said voltage-sensitive switch transistor is coupled to a point of reference potential.

Claim 13

A delayed transistor blanking pulse generator according to claim 9 wherein said voltage-sensitive switch means further comprises a second transistor emitter-coupled to said voltage-sensitive switch transistor and having its base electrode coupled to a source of reference potential; a current source coupled to the joined emitters of said second and voltage-sensitive switch transistors for supplying operating current thereto; and unidirectional current conducting means coupled from a source of reference potential to said joined emitters.

Claim 14

A delayed transistor blanking pulse generator according to claim 9 wherein said collector load means comprises constant-current source means.

Claim 15

A delayed transistor blanking pulse generator in accordance with claim 13 wherein said collector load means comprises a constant-current source.

Claim 16

A delayed blanking pulse generator comprising: resistance means coupled to a source of operating potential; biasing means coupled in series with said resistance means; a first transistor having a base-emitter junction coupled across said biasing means thereby forming at its collector electrode a first current source; capacitance means coupled to said collector electrode of said first transistor at a first point for being charged therefrom, and forming a ramp voltage; second transistor means having a base electrode coupled to said point, a collector electrode coupled to an output terminal of the blanking pulse generator for initiating a blanking pulse when said ramp voltage reaches a first value; third transistor means having a controlled conduction path coupled in parallel with said capacitor for discharge thereof and having a control electrode; fourth transistor means having a base-emitter junction coupled in parallel with said base-emitter junction of said first transistor for producing a constant collector current; second biasing means coupled to said collector of said fourth transistor means and to said control electrode of said third transistor means for conditioning said third transistor means for conduction; controllable switch means coupled in parallel with said second biasing means and having a control electrode coupled to a source of undelayed blanking pulses for periodically inhibiting conduction of said third transistor means; fifth transistor means having a base-emitter junction coupled in parallel with said base-emitter junction of said third transistor means for being conditioned for conduction therewith; sixth transistor means having an emitter electrode coupled to a collector electrode of said fifth transistor means, a base electrode coupled to said first point and a collector electrode coupled to said output terminal; and seventh transistor means having a base-emitter junction coupled to said first biasing means for being conditioned for conduction and a collector electrode coupled to said output terminal.

Claim 17

A delayed blanking pulse generator comprising: resistance means coupled to a source of operating potential; biasing means coupled in series with said resistance means; a first transistor having a base-emitter junction coupled across said biasing means thereby forming at its collector electrode a first current source; capacitance means coupled to said collector electrode of said first transistor at a first point for being charged therefrom, and forming a ramp voltage; second transistor means having a base electrode coupled to said point, a collector electrode coupled to an output terminal of the blanking pulse generator for initiating a blanking pulse when said ramp voltage reaches a first value; third transistor means having a controlled conduction path coupled in parallel with said capacitor for discharge thereof and having a control electrode; fourth transistor means having a base-emitter junction coupled in parallel with said base-emitter junction of said first transistor for producing a constant collector current; second biasing means coupled to said collector of said fourth transistor means and to said control electrode of said third transistor means for conditioning said third transistor means for conduction; controllable switch means coupled in parallel with said second biasing means and having a control electrode coupled to a source of undelayed blanking pulses for periodically inhibiting conduction of said third transistor means; fifth transistor means having a base-emitter junction coupled in parallel with said base-emitter junction of said third transistor means for being conditioned for conduction therewith; sixth transistor means having an emitter electrode coupled to a collector electrode of said fifth transistor means, a base electrode coupled to said first point and a collector electrode coupled to said output terminal; and seventh transistor means having a base-emitter junction coupled to said first biasing means for being conditioned for conduction and a collector electrode coupled to said output terminal.